71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
AUGUST 2007
On-Chip Resources
DIO Ports
The 71M6511/6511H includes up to 12 pins of general purpose digital I/O. These pins are dual function and can alternatively
be used as LCD drivers. Figure 8 shows a block diagram of the DIO section.
On reset or power-up, all DIO pins are inputs until they are configured for the desired direction. The pins are configured and
controlled by the DIO and DIO_DIR registers (SFRs) and by the five bits of the I/O register LCD_NUM (0x2020[4:0]). See the
description for LCD_NUM in the I/O RAM Section for a table listing the available segment pins versus DIO pins, depending on
the selection for LCD_NUM. Generally, increasing the value for LCD_NUM will configure an increasing number of general
purpose pins to be LCD segment pins, starting at the higher pin numbers.
LCD DISPLAY
DRIVER
COM0..3
SEG0..SEG2
SEG8..SEG19
LCD_NUM
LCD_MODE
LCD_CLK
LCD_EN
SEG24/DIO4 ...
SEG31/DIO11
SEG34/DIO14 ...
SEG37/DIO17
DIGITAL I/O
DIO_EEX
PULSEV/W
DIO_IN
SEG3/SCLK
SEG4/SSDATA
SEG5/SFR
SEG6/SRDY
SEG7/
DIO_OUT
LCD_NUM
DIO_GP
MUX_SYNC
Figure 8: DIO Ports Block Diagram
Each pin declared as DIO can be configured independently as an input or output with the bits of the DIO_DIRn registers. Table
52 lists the direction registers and configurability associated with each group of DIO pins. Table 53 shows the configuration for
a DIO pin through its associated bit in its DIO_DIR register.
DIO
0
--
--
1
--
--
2
--
--
3
--
--
4
5
6
7
8
9
10 11 12 13 14 15
Pin number
37 38 39 40 41 42 43 44
--
--
--
--
20 21
4
5
6
6
7
7
0
0
1
1
2
3
6
6
7
7
Data Register bit
DIO0=P0 (SFR 0x80)
DIO1=P1 (SFR 0x90)
Direction Register
bit
--
--
--
--
--
--
4
5
2
3
--
--
DIO_DIR0 (SFR 0xA2)
DIO_DIR1 (SFR 0x91)
Internal Resources
-- --
Y
Y
Y
Y
Y
Y
Y
Y
-- --
N
N
Configurable
DIO
16 17 18 19 20 21 22 23
Pin number
22 12
--
--
--
--
--
--
--
--
--
--
--
--
0
0
1
1
Data Register bit
DIO2=P2 (SFR 0xA0)
Direction Register
bit
--
--
--
--
--
--
--
--
DIO_DIR2 (SFR 0xA1)
Internal Resources
N
N
-- -- -- --
Configurable
Table 52: Data/Direction Registers and Internal Resources for DIO Pin Groups
Page: 36 of 95
© 2005-2007 TERIDIAN Semiconductor Corporation
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