71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
AUGUST 2007
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 46:
Group
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
-
Serial channel 1 interrupt
0
1
2
3
4
5
-
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
-
-
-
-
Table 46: Priority Level Groups
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the
special function register IP0 and one in IP1. If requests of the same priority level are received simultaneously, an internal
polling sequence as per Table 50 determines which request is serviced first.
IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that is set by
the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). XFER_BUSY and RTC_1SEC,
which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6 enable and flag bits (see Table 45),
and these interrupts must be cleared by the MPU software.
An overview of the interrupt structure is given in Figure 7.
Interrupt Priority 0 Register (IP0)
MSB
LSB
IP0.0
--
WDTS
IP0.5
Table 47: The IP0 Register:
Note: WDTS is not used for interrupt controls
IP0.4
IP0.3
IP0.2
IP0.1
IP1.1
Interrupt Priority 1 Register (IP1)
MSB
LSB
IP1.0
-
-
IP1.5
IP1.4
IP1.3
IP1.2
Table 48: The IP1 Register:
IP1.x
IP0.x
Priority Level
Level0 (lowest)
Level1
Level2
Level3 (highest)
0
0
1
1
0
1
0
1
Table 49: Priority Levels
Page: 33 of 95
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