71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
AUGUST 2007
Timer/Counter Control register (TCON)
MSB
LSB
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Table 40: The TCON Register
Bit
TCON.7
Symbol
Function
Timer 1 overflow flag
Not used for interrupt control
Timer 0 overflow flag
Not used for interrupt control
External interrupt 1 flag
External interrupt 1 type control bit
External interrupt 0 flag
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TCON.6
TCON.5
TCON.4
TCON.3
TCON.2
TCON.1
TCON.0
External interrupt 0 type control bit
Table 41: The TCON Bit Functions
Interrupt Request register (IRCON)
MSB
LSB
EX6
IEX5
IEX4
IEX3
IEX2
Table 42: The IRCON Register
Bit
IRCON.7
Symbol
Function
-
IRCON.6
IRCON.5
IRCON.4
IRCON.3
IRCON.2
IRCON.1
IRCON.0
-
IEX6
IEX5
IEX4
IEX3
IEX2
-
External interrupt 6 edge flag
External interrupt 5 edge flag
External interrupt 4 edge flag
External interrupt 3 edge flag
External interrupt 2 edge flag
Table 43: The IRCON Bit Functions
Note: Only TF0 and TF1 (timer 0 and timer 1 overflow flag) will be automatically cleared by hardware when the service routine
is called (Signals T0ACK and T1ACK – port ISR – active high when the service routine is called).
External Interrupts
The external interrupts are connected as shown in Table 44. The polarity of interrupts 2 and 3 is programmable in the MPU.
Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU literature states that interrupts 4
through 6 are defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted to
achieve the edge polarity shown in Table 44.
SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has
its own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5).
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