71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
AUGUST 2007
VREF VBIAS
IA
VA
IB
∆Σ ADC
CONVERTER
MUX
VBIAS
VREF
-
V3P3A
FIR
+
FILTER
VREF
FIR_LEN
CHOP_EN
VREF_DIS
MUX
TEMP
MUX
CTRL
CK32
EQU
MUX_ALT
MUX_DIV
Figure 3: AFE Block Diagram
Computation Engine (CE)
The CE, a dedicated 32-bit RISC processor, performs the precision computations necessary to accurately measure energy.
The CE calculations and processes include:
•
Multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when
multiplied with the constant sample time).
•
Frequency-insensitive delay cancellation on all six channels (to compensate for the delay between samples caused
by the multiplexing scheme).
•
•
•
•
•
90° phase shifter (for VAR calculations).
Pulse generation.
Monitoring of the input signal frequency (for frequency and phase information).
Monitoring of the input signal amplitude (for sag detection).
Scaling of the processed samples based on chip temperature (temperature compensation) and calibration
coefficients.
The CE program RAM (CE PRAM) is loaded at boot time by the MPU and then executed by the CE. Each CE instruction word
is 2 bytes long. The CE program counter begins a pass through the CE code each time multiplexer state 0 begins. The code
pass ends when a HALT instruction is executed. For proper operation, the code pass must be completed before the
multiplexer cycle ends (see System Timing Summary in the Functional Description Section).
The CE data RAM (CE DRAM) can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time
slots are reserved for FIR, RTM, and MPU, respectively, such that memory accesses to CE_RAM do not collide. Holding re-
gisters are used to convert 8-bit wide MPU data to/from 32-bit wide CE DRAM data, and wait states are inserted as needed,
depending on the frequency of CKMPU.
Table 3 shows the CE DRAM addresses allocated to analog inputs from the AFE.
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