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71M6511H-IGTR 参数 Datasheet PDF下载

71M6511H-IGTR图片预览
型号: 71M6511H-IGTR
PDF下载: 下载PDF文件 查看货源
内容描述: 单相电能计量芯片 [Single-Phase Energy Meter IC]
分类和应用:
文件页数/大小: 95 页 / 860 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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71M6511/71M6511H  
Single-Phase Energy Meter IC  
DATA SHEET  
AUGUST 2007  
Digital Pins:  
Name  
Pin #  
Type  
O
Circuit  
Description  
COM3,  
16  
COM2,  
15  
14  
LCD Common Outputs: These 4 pins provide the select signals for the  
LCD display.  
5
5
COM1,  
COM0  
13  
SEG19…SEG8,  
SEG2…SEG0  
SEG24/DIO4…  
SEG31/DIO11,  
SEG34/DIO14…  
SEG37/DIO17  
SEG7/  
See  
pinout  
O
Dedicated LCD Segment Output pins.  
Multi-use pins, configurable as either LCD SEG driver or DIO (DIO4 =  
SCK, DIO5 = SDA when configured as EEPROM interface, WPULSE  
= DIO6, VARPULSE = DIO7 when configured as pulse outputs). If  
unused, these pins must be configured as outputs.  
Multi-use-pin LCD Segment Output/ MUX_SYNC is output for  
Synchronous serial interface  
See  
O
3, 4, 5  
pinout  
24  
23  
O
4, 5  
2, 5  
MUX_SYNC  
Multi-use-pin, LCD Segment Outputs/ SRDY input for Synchronous  
serial interface. When configured as SRDY, this pin must be pulled  
down to GNDD.  
SEG6/SRDY  
I/O  
Multi-use-pin, LCD Segment Output/ SFR output for Synchronous  
serial interface.  
SEG5/SFR  
11  
10  
6
O
O
O
4, 5  
4, 5  
4, 5  
Multi-use-pin, LCD Segment Output/ SDATA output for Synchronous  
serial interface.  
SEG4/SDATA  
Multi-use-pin, LCD Segment Output/ SCLK output for Synchronous  
serial interface.  
SEG3/SCLK  
CKTEST  
TMUXOUT  
8
4
O
O
4
4
Clock PLL output. Can be enabled and disabled by CKOUT_DIS.  
Digital output test multiplexer. Controlled by DMUX[3:0].  
Optical Receive Input: This pin may receive a signal from an external  
photo-detector used in an IR serial interface. If this pin is unused it  
must be terminated to V3P3D or GNDD.  
OPT_RX  
57  
I
7
Optical LED Transmit Output: This pin is designed to directly drive an  
LED for transmitting data in an IR serial interface. Can be tristated with  
OPT_TXDIS to be multiplexed with other DIO pins.  
This input pin resets the chip into a known state. For normal operation,  
this pin is set to 1. To reset the chip, this pin is driven to 0. This pin  
has an internal 30µA (nominal) current source pull up. A 0.1µF ca-  
pacitor to GNDD should be connected to this pin. See the precau-  
tions in the Applications Section for terminating this pin.  
UART input. The voltage applied at this input must be below 3.6V.  
If this pin is unused it must be terminated to V3P3D or GNDD.  
UART output.  
OPT_TX  
3
O
4
RESETZ  
RX  
48  
45  
I
I
1
3
TX  
E_RXTX  
E_TCLK  
5
2
64  
O
I/O  
O
4
1, 4  
4
Emulator serial data. This pin has an internal pull-up resistor.  
Emulator clock.  
Emulator reset. This pin has an internal pull-up resistor. See the  
precautions in the Applications Section for terminating this pin.  
Enables Production Test. This pin must be grounded in normal  
operation.  
E_RST  
63  
I/O  
1, 4  
TEST  
60  
I
7
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output  
The circuit number denotes the equivalent circuit, as specified on the following page.  
Page: 93 of 95  
© 2005-2007 TERIDIAN Semiconductor Corporation  
V2.6  
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