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71M6511H-IGTR 参数 Datasheet PDF下载

71M6511H-IGTR图片预览
型号: 71M6511H-IGTR
PDF下载: 下载PDF文件 查看货源
内容描述: 单相电能计量芯片 [Single-Phase Energy Meter IC]
分类和应用:
文件页数/大小: 95 页 / 860 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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71M6511/71M6511H  
Single-Phase Energy Meter IC  
DATA SHEET  
AUGUST 2007  
80515 MPU Core  
80515 Overview  
The 71M6511/6511H includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle.  
Using a 5MHz clock results in a processing throughput of 5 MIPS. The 80515 architecture eliminates redundant bus states and  
implements parallel execution of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, there-  
fore, most of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (in average) improvement  
(in terms of MIPS) over the Intel 8051 device running at the same clock frequency.  
Actual processor clocking speed can be adjusted to the total processing demand of the application (metering calculations,  
AMR management, memory management, LCD driver management and I/O management) using the I/O RAM register  
MPU_DIV[2:0].  
Typical measurement and metering functions based on the results provided by the internal 32-bit compute engine (CE) are  
available for the MPU as part of TERIDIAN’s standard library. A standard ANSI “C” 80515-application programming interface  
library is available to help reduce design cycle.  
Memory Organization  
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces.  
Memory organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas: Program  
memory (Flash), external data memory (XRAM), physically consisting of XRAM, CE DRAM, CE PRAM and I/O RAM, and  
internal data memory (Internal RAM). Figure 6 shows the memory map (see also Table 55).  
Internal and External Data Memory: Both internal and external data memory are physically located on the 71M6511 IC. Ex-  
ternal data memory is only external to the 80515 MPU core.  
0xFFFF  
0xFFFF  
0x4000  
0x3FFF  
0x3000  
0x2FFF  
0x2100  
0x20FF  
0x2000  
0x1FFF  
0x1400  
0x13FF  
0x1000  
0x0FFF  
0x0800  
0x07FF  
0x0000  
---  
CE PRAM  
---  
I/O RAM  
---  
Flash memory  
CE DRAM  
---  
0xFF  
0x00  
SFRs, RAM,  
reg. banks  
XRAM  
0x0000  
Program memory  
External data memory  
Internal data memory  
Figure 6: Memory Map  
Program Memory: The 80515 can address up to 64KB of program memory space from 0x0000 to 0xFFFF. Program memory  
is read when the MPU fetches instructions or performs a MOVC operation.  
After reset, the MPU starts program execution from location 0x0000. The lower part of the program memory includes reset and  
interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting from 0x0003.  
Page: 15 of 95  
© 2005-2007 TERIDIAN Semiconductor Corporation  
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