71M6403
Electronic Trip Unit
SEPTEMBER 2006
Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter or timer
operations.
In timer mode, the register is incremented every machine cycle meaning that it counts up after every 12 periods of the MPU
clock signal.
In counter mode, the register is incremented when the falling edge is observed at the corresponding input signal T0 or T1 (T0
and T1 are the timer gating inputs derived from certain DIO pins, see the DIO Ports chapter). Since it takes 2 machine cycles to
recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator frequency. There are no restrictions on the duty
cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers (TMOD and TCON) are used to
select the appropriate mode.
Timer/Counter Mode Control register (TMOD):
MSB
LSB
M0
GATE
C/T
M1
M0
GATE
C/T
M1
Timer 1
Timer 0
Table 17: The TMOD Register
Bits TR1 and TR0 start their associated timers when set.
Bit
Symbol
Function
TMOD.7
TMOD.3
Gate
If set, enables external gate control (pin int0 or int1 for Counter 0 or 1,
respectively). When int0 or int1 is high, and TRX bit is set (see TCON register), a
counter is incremented every falling edge on t0 or t1 input pin
TMOD.6
TMOD.2
TMOD.5
TMOD.1
TMOD.4
TMOD.0
C/T
M1
M0
Selects Timer or Counter operation. When set to 1, a Counter operation is
performed. When cleared to 0, the corresponding register will function as a Timer.
Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD
description.
Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD
description.
Table 18: TMOD Register Bit Description
Page: 24 of 75
© 2006 TERIDIAN Semiconductor Corporation
REV 1.0
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