71M6403
Electronic Trip Unit
SEPTEMBER 2006
Zero
Address
Name
Description
Reference
0x00
0x01
0x02
0x03
0x04
0x05
0x06
I0
I1
I2
I3
I4
I5
V3P3
V3P3
V3P3
V3P3
V3P3
V3P3
---
Current input 0
Current input 1
Current input 2
Current input 3
Current input 4
Current input 5
Temperature
TEMP
INEUTRAL
monitor
0x07
INEUTRAL
VBIAS
Table 2: CE DRAM Locations for ADC Results
CE Functional Overview
The ADC processes one sample per channel per multiplexer cycle. Figure 4 shows the timing of the six samples taken during
one multiplexer cycle.
The ADC sampling process and resultant accumulation interval calculations are described in the CE Program section.
1/2520.6Hz = 397µs
I2
I3
I4
I5
I0
2/32768Hz =
61.04µs
I1
13/32768Hz = 397µs
per mux cycle
Figure 4: Samples in Multiplexer Cycle
Page: 12 of 75
© 2006 TERIDIAN Semiconductor Corporation
REV 1.0
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
