78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit
PIN DESCRIPTION (CONTINUED)
RECEIVER PINS
NAME
PIN
TYPE DESCRIPTION
Receive Parallel Data Output:
46, 51
45, 52
42, 55
41, 56
POx0D
POx1D
POx2D
POx3D
Recovered receive data deserialized into four-bit CMOS parallel (nibble)
outputs. The MSB (POx3D) is received first. Active, but undefined during
reset.
CO
Note: During Loss of Signal conditions, data outputs are held low.
Receive Parallel Clock Output:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock output generated by
dividing down the recovered receive clock. By default, receive data is
clocked out on the falling edge. Active during reset.
38, 59
CO
POxCK
Note: During Loss of Signal conditions, the clock automatically switches to a
34.816MHz (E4) or 38.88MHz (STM1) clock generated from the reference
clock.
Receive Serial Data Output:
Recovered receive serial NRZ data. Active, but undefined during reset.
Note: During Loss of Signal conditions, data outputs are held low.
28, 69
29, 68
SOxDP
SOxDN
PO
PO
Receive Serial Clock Output:
Recovered receive serial clock. By default, recovered serial NRZ data is
25, 72
26, 71
SOxCKP
SOxCKN
clocked out the falling edge of SOxCKP. Active during reset.
Note: During Loss of Signal conditions, the clock automatically switches to a
divided down reference clock of 34.816MHz (E4) or 38.88MHz (STM1).
Receive Serial CMI or LVPECL Input:
118, 107
119, 106
A/
PI
RXxP
RXxN
The input signal is either differentially terminated and transformer coupled for
CMI data or at LVPECL levels for NRZ data.
16
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
