78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit
PIN DESCRIPTION
LEGEND
TYPE
DESCRIPTION
TYPE DESCRIPTION
Analog Pin
LVPECL-Compatible Differential Output
A
PO
CO
COZ
OD
S
(Tie unused pins to ground)
(Tie unused pins to supply or leave floating)
CMOS Digital Output
CIT
CI
3-State CMOS Digital Input
(Leave unused pins floating)
CMOS Digital Input
CMOS Tristate Digital Output
(Tie unused pins to ground)
(Leave unused pins floating)
Open-drain Digital Output
CIU
CID
CIS
PI
CMOS Digital Input w/ Pull-up
(Leave unused pins floating)
CMOS Digital Input w/ Pull-down
Supply
Ground
CMOS Schmitt Trigger Input
G
(Tie unused pins to ground)
LVPECL-Compatible Differential Input
(Tie unused pins to ground)
TRANSMITTER PINS
NAME
PIN
TYPE DESCRIPTION
Transmit Parallel Data Input:
31, 66
32, 65
33, 64
34, 63
PIx0D
PIx1D
PIx2D
PIx3D
Four-bit CMOS parallel (nibble) inputs. Data is latched in on the rising edge
(default) of the transmit parallel clock and serialized with the MSB (PIx3D)
transmitted first.
CI
Transmit Parallel Clock Input:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock input that must be
source synchronous with the reference clock supplied at the CKREFP/N pins.
Used in Slave Parallel Mode.
30, 67
35, 62
CIS
CO
PIxCK
Transmit Parallel Clock Output:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock output that is
intended to latch in synchronous parallel data. Active during reset. Used in
Master Parallel Mode.
PTOxCK
Transmit Serial Data Input:
10, 87
11, 86
SIxDP
SIxDN
PI
PI
Differential NRZ data input. See Transmitter Operation section for more info
on different clocking/timing modes.
Transmit Serial Clock Input:
7, 90
8, 89
SIxCKP
SIxCKN
A 155.52MHz synchronous differential input clock used to clock in the serial
NRZ data. By default, data is clocked in on the rising edge of SIxCKP.
Transmit Serial CMI Data Output:
A CMI encoded data signal conforming to the relevant ITU-T G.703 pulse
templates when properly terminated and transformer coupled to 75ohm
cable. Outputs are tri-stated when transmitter is disabled. Active, but
undefined during reset.
121, 104
122, 103
CMIxP
CMIxN
A
Transmit Serial Clock Output:
124, 101
125, 100
TXxCKP
TXxCKN
PO
PO
An optional 2x line rate LVPECL clock output used to clock out the transmit
CMI data. Used for diagnostics or far end re-timing. Active during reset.
127, 98
128, 97
Transmit Serial LVPECL Data Output:
Transmit NRZ data used for interfacing with optical transceiver modules.
ECLxP
ECLxN
15
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
