TSC80C31/80C51
External Data Memory Characteristics (values in ns)
16 MHz 20 MHz 25 MHz 30 MHz 36 MHz 40 MHz 44 MHz
min max min max min max min max min max min max min max
SYMBOL
PARAMETER
TRLRH
RD pulse Width
340
340
85
270
270
85
210
210
70
180
180
55
120
120
35
100
100
30
80
80
25
TWLWH WR pulse Width
TLLAX
TRLDV
TRHDX
TRHDZ
TLLDV
TAVDV
TLLWL
TAVWL
Address Hold After ALE
RD to Valid data in
Data hold after RD
Data float after RD
ALE to Valid Data In
Address to Valid Data IN
ALE to WR or RD
240
210
175
135
110
90
70
0
0
0
0
0
0
0
90
90
80
70
50
45
150
180
95
35
130
170
85
435
480
370
400
350
300
235
260
115
170
190
100
150 250 135 170 120 130
90
115
20
70
75
60
65
50
55
6
Address to WR or RD
180
35
180
35
140
30
TQVWX Data valid to WR transition
TQVWH Data Setup to WR transition
TWHQX Data Hold after WR
15
10
380
40
325
35
250
30
215
20
170
15
160
10
140
6
TRLAZ
RD low to Address Float
0
0
0
0
0
0
0
TWHLH RD or WR high to ALE high
35
90
35
60
25
45
20
40
20
40
15
35
13
33
External Data Memory Write Cycle
TAVWL
TQVWX
External Data Memory Read Cycle
MATRA MHS
15
Rev. E (14 Jan.97)
TEMIC [ TEMIC SEMICONDUCTORS ]
