TS80C52X2
For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins
to float when a 100 mV change from the loaded V /V level occurs. I /I
≥ ± 20mA.
OH OL
OL OH
10.4.15 Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two.
STATE1
P1 P2
STATE2
STATE3
STATE4
P1 P2 P1
STATE4
P1 P2
STATE5
P1 P2
STATE6
P1 P2
STATE5
INTERNAL
CLOCK
P1
P2 P1 P2
P2
XTAL2
ALE
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
EXTERNAL PROGRAM MEMORY FETCH
PSEN
PCL OUT
PCL OUT
PCL OUT
DATA
P0
DATA
SAMPLED
DATA
SAMPLED
SAMPLED
FLOAT
FLOAT
FLOAT
INDICATES ADDRESS TRANSITIONS
P2 (EXT)
READ CYCLE
RD
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
P0
P2
DPL OR Rt OUT
FLOAT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
WRITE CYCLE
WR
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
P0
DPL OR Rt OUT
DATA OUT
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P2
PORT OPERATION
OLD DATA
P0 PINS SAMPLED
NEW DATA
P0 PINS SAMPLED
MOV DEST P0
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
P1, P2, P3 PINS SAMPLED
MOV DEST PORT (P1, P2, P3)
(INCLUDES INT0, INT1, TO, T1)
RXD SAMPLED
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
Figure 25. Clock Waveforms
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (T =25°C fully loaded)
A
RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays
are incorporated in the AC specifications.
Rev. B - Jan. 25, 1999
53
Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
