TS80C52X2
10.4.6 External Data Memory Read Cycle
T
WHLH
T
ALE
PSEN
RD
LLDV
T
T
RLRH
LLWL
T
RHDZ
T
AVDV
T
T
LLAX
RHDX
PORT 0
PORT 2
A0-A7
DATA IN
T
RLAZ
T
AVWL
ADDRESS
OR SFR-P2
ADDRESS A8-A15 OR SFR P2
Figure 19. External Data Memory Read Cycle
10.4.7 Serial Port Timing - Shift Register Mode
Table 30. Symbol Description
Symbol
Parameter
T
T
T
Serial port clock cycle time
XLXL
QVHX
XHQX
Output data set-up to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
TXHDX
T
Clock rising edge to input data valid
XHDV
Table 31. AC Parameters for a Fix Clock
Speed
-M
-V
-L
Units
(see ordering)
Symbol
Min
300
200
20
Max
Min
200
117
13
Max
Min
600
367
50
Max
T
ns
ns
ns
ns
ns
XLXL
QVHX
XHQX
XHDX
XHDV
T
T
T
T
0
0
0
200
117
367
Rev. B - Jan. 25, 1999
49
Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
