80C154/83C154
External Data Memory Characteristics
16 MHz
20 MHz
25 MHz
30 MHz
36 MHz
SYMBOL
TRLRH
TWLWH
TLLAX
TRLDV
TRHDX
TRHDZ
TLLDV
TAVDV
TLLWL
TAVWL
TQVWX
TQVWH
TWHQX
TRLAZ
TWHLH
PARAMETER
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
RD pulse Width
340
340
85
270
270
85
210
210
70
180
180
55
120
120
35
WR pulse Width
Address Hold After ALE
RD to Valid in
240
210
175
135
110
Data hold after RD
0
0
0
0
0
Data float after RD
90
90
80
70
50
ALE to Valid Data In
Address to Valid Data IN
ALE to WR or RD
435
480
250
370
400
170
350
300
130
235
260
115
170
190
100
150
180
35
135
180
35
120
140
30
90
115
20
70
75
Address to WR or RD
Data valid to WR transition
Data Setup to WR transition
Data Hold after WR
15
380
40
325
35
250
30
215
20
170
15
RD low to Address Float
RD or WR high to ALE high
0
0
0
0
0
35
90
35
60
25
45
20
40
20
40
External Data Memory Write Cycle
TAVWL
TQVWX
External Data Memory Read Cycle
20
MATRA MHS
Rev.F (14 Jan. 97)
TEMIC [ TEMIC SEMICONDUCTORS ]
