L67132/L67142
AC Parameters
L67132–45
L67142–45
L67132–55
L67142–55
L67132–70
L67142–70
READ CYCLE
PARAMETER
UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
SYMBOL SYMBOL
(19)
(20)
PRELIMINARY
TAVAVR
TAVQV
TELQV
TGLQV
TAVQX
TELQZ
TEHQZ
TPU
t
t
t
t
t
t
t
t
t
Read cycle time
45
–
–
45
45
30
–
55
–
70
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address access time
–
–
–
0
5
–
0
–
55
55
35
–
–
–
–
0
5
–
0
–
70
70
40
–
AA
ACS
AOE
OH
LZ
Chip Select access time (18)
Output enable access time
–
–
Output hold from address change
Output low Z time (16, 17)
Output high Z time (16, 17)
Chip Select to power up time (17)
Chip disable to power down time (17)
0
5
–
–
–
–
20
–
30
–
35
–
HZ
0
PU
TPD
–
50
50
50
PD
Notes : 16. Transition is measured ± 500 mV from low or high impedance voltage with load (figures 1 and 2).
17. This parameter is guaranteed but not tested.
18. To access RAM CS = VIL.
19. STD symbol.
20. ALT symbol.
Timing Waveform of Read Cycle no 1, Either Side (21, 22, 24)
Timing Waveform of Read Cycle no 2, Either Side (21, 23, 25)
Notes : 21. R/W is high for read cycles.
22. Device is continuously enabled, CS = VIL.
23. Addresses valid prior to or coincident with CS transition low.
24. OE = V
.
IL
25. To access RAM, CS = V
.
IL
MATRA MHS
Rev. D (19 Fev. 97)
7
TEMIC [ TEMIC SEMICONDUCTORS ]
