L67132/L67142
Data-Retention Mode
MHS CMOS RAMs are designed with battery backup in 2 – CS must be kept between V – 0.2 V and 70 % of Vcc
CC
mind. Data retention voltage and supply current are during the power up and power down transitions.
guaranteed over temperature. The following rules insure
data retention :
3 – The RAM can begin operation > tRC after Vcc
reaches the minimum operating voltage (3 volts).
1 – Chip select (CS) must be held high during data
retention ; within Vcc to VCC
.
DR
Timing
MAX
MIL
IND
PARAMETER
TEST CONDITIONS (14)
UNIT
COM
AUTO
ICC
@ VCC = 2 V
10
20
µA
DR1
DR
Notes : 14. CS = Vcc, Vin = Gnd to Vcc.
AC Test Conditions
Input Pulse Levels : GND to 3.0 V
Input Rise/Fall Times : 5 ns
Output Reference Levels : 1.5 V
Output Load : see figures 1, 2
Input Timing Reference Levels : 1.5 V
Figure 1. Output Load.
Figure 2. Output load.
(For t , t , t , and t
)
HZ LZ WZ
OW
6
MATRA MHS
Rev. D (19 Fev. 97)
TEMIC [ TEMIC SEMICONDUCTORS ]
