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80C32-25 参数 Datasheet PDF下载

80C32-25图片预览
型号: 80C32-25
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS 0至44 MHz的单芯片8位Microntroller [CMOS 0 to 44 MHz Single Chip 8?bit Microntroller]
分类和应用:
文件页数/大小: 20 页 / 221 K
品牌: TEMIC [ TEMIC SEMICONDUCTORS ]
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80C32/80C52  
Explanation of the AC Symbol  
Each timing symbol has 5 characters. The first character Example :  
is always a “T” (stands for time). The other characters,  
TAVLL = Time for Address Valid to ALE low.  
TLLPL = Time for ALE low to PSEN low.  
depending on their positions, stand for the name of a  
signal or the logical status of that signal. The following  
is a list of all the characters and what they stand for.  
A : Address.  
C : Clock.  
D : Input data.  
Q : Output data.  
R : READ signal.  
T : Time.  
H : Logic level HIGH  
I : Instruction (program memory contents).  
L : Logic level LOW, or ALE.  
P : PSEN.  
V : Valid.  
W : WRITE signal.  
X : No longer a valid logic level.  
Z : Float.  
AC Parameters  
TA = 0 to + 70°C ; Vss = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 44 MHz  
TA = 0 to +70°C ; Vss = 0 V ; 2.7 V < Vcc < 5.5 V ; F = 0 to 16 MHz  
TA = –40° to + 85°C ; Vss = 0 V ; 2.7 V < Vcc < 5.5 V ; F = 0 to 16 MHz  
TA = –55° + 125°C ; Vss = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz  
(Load Capacitance for PORT 0, ALE and PSEN = 100 pF ; Load Capacitance for all other outputs = 80 pF)  
External Program Memory Characteristics (values in ns)  
16 MHz 20 MHz 25 MHz 30 MHz 36 MHz 40 MHz 42 MHz 44 MHz  
min max min max min max min max min max min max min max min max  
SYM-  
BOL  
PARAMETER  
TLHLL ALE Pulse Width  
110  
40  
90  
30  
35  
70  
20  
35  
60  
15  
35  
50  
10  
35  
40  
9
35  
8
30  
7
TAVLL Address valid to ALE  
TLLAX Address Hold After ALE  
35  
30  
25  
17  
TLLIV  
ALE to valid instr in  
185  
170  
130  
100  
80  
70  
65  
65  
TLLPL ALE to PSEN  
45  
40  
30  
25  
80  
20  
75  
15  
65  
13  
60  
12  
54  
TPLPH PSEN pulse Width  
165  
130  
100  
TPLIV  
TPXIX  
TPXIZ  
PSEN to valid instr in  
125  
50  
110  
45  
85  
35  
65  
30  
50  
25  
45  
20  
40  
15  
35  
10  
Input instr Hold After PSEN  
Input instr Float After PSEN  
0
0
0
0
0
0
0
0
TPXAV PSEN to Address Valid  
TAVIV Address to Valid instr in  
TPLAZ PSEN low to Address Float  
55  
50  
40  
35  
30  
25  
20  
15  
230  
10  
210  
10  
170  
8
130  
6
90  
5
80  
5
75  
5
70  
5
External Program Memory Read Cycle  
TAVIV  
MATRA MHS  
15  
Rev. G (14 Jan. 97)  
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