100mA CHARGE PUMP DC-TO-DC
VOLTAGECONVERTER
1
2
3
4
5
6
7
8
TC660
+
V
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
+
TC660
"1"
150 µF
+
TC660
"n"
150 µF
V
*
OUT
150 µF
+
150 µF
+
+
+
. V
NOTE:
= –n(V ) for 1.5V ≤ V ≤ 5.5V
*
OUT
Figure 5. Increased Output Voltage by Cascading Devices
clock frequency using TTL logic, the addition of a 10kΩ pull-
up resistor to V+ supply is required. Note that the pump
frequency with external clocking, as with internal clocking,
willbe1/2oftheclockfrequency.Outputtransitionsoccuron
the positive-going edge of the clock.
Cascading Devices
The TC660 may be cascaded as shown (Figure 5) to
produce larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
the practical limit is 10 devices for light loads. The output
voltage is defined by:
It is also possible to increase the conversion efficiency
of the TC660 at low load levels by lowering the oscillator
frequency.Thisreducestheswitchinglosses,andisachieved
by connecting an additional capacitor, COSC, as shown in
Figure 7. Lowering the oscillator frequency will cause an
undesirableincreaseintheimpedanceofthepump(C1)and
thereservoir(C2)capacitors.Toovercomethis,increasethe
values of C1 and C2 by the same factor that the frequency
has been reduced. For example, the addition of a 100pF
capacitor between pin 7 (OSC) and GND will lower the
oscillator frequency to 1kHz from its nominal frequency of
10kHz (a multiple of 10), and necessitate a corresponding
increase in the values of C1 and C2.
VOUT = –n (VIN)
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be ap-
proximately the weighted sum of the individual TC660 ROUT
values.
Changing the TC660 Oscillator Frequency
Itmaybedesirableinsomeapplications(duetonoiseor
other considerations) to increase the oscillator frequency.
Pin 1, the FC pin, may be connected to V+ to increase
oscillator frequency to 90kHz from a nominal of 10 kHz for
an input supply voltage of 5.0 volts. The oscillator may also
be synchronized to an external clock as shown in Figure 6
and LV must be grounded when overdriving OSC. In a
situation where the designer has generated the external
Positive Voltage Doubler
+
V
1
2
3
4
8
7
6
5
+
+
V
V
1
2
3
4
8
7
6
5
C
+
OSC
TC660
OSC
C
1
CMOS
GATE
V
+
OUT
TC660
150 µF
C
2
+
V
OUT
150 µF
+
Figure 7. Lowering Oscillator Frequency
Figure 6. External Clocking
TELCOM SEMICONDUCTOR, INC.
4-11
TELCOM [ TELCOM SEMICONDUCTOR, INC ]
