5V PRECISION DATA ACQUISITION
SUBSYSTEMS
TC530
TC534
Auto Zero Phase
(AZ)
This phase compensates for errors due to buffer, inte-
grator and comparator offset voltages. During this phase, an
internal feedback loop forces a compensating error voltage
on auto zero capacitor (C
AZ
). The duration of the AZ phase
is programmable via the serial port (see also Programming
AZ and INT Phase Duration paragraph of this document).
Input Integrate Phase
(INT)
In this phase, a current directly proportional to differen-
tial input voltage is sourced into integrating capacitor C
INT
.
The amount of voltage stored on C
INT
at the end of the INT
phase is directly proportional to the applied differential input
voltage. Input signal polarity (sign bit) is determined at the
end of this phase. Converter resolution and conversion
speed is a function of the duration of the INT phase, which
is programmable by the user via the serial port (see also
Programming AZ and INT Phase Duration paragraph of this
document). The shorter the integration time, the faster the
speed of conversion, but the lower the resolution. Con-
versely, the longer the integration time, the greater the
resolution, but at slower the speed of conversion.
Reference Deintegrate Phase
(DINT)
This phase consists of measuring the time for the
integrator output to return (at a rate determined by the
external reference voltage) from its initial voltage to 0V. The
resulting timer data is stored in the output shift register as
converted analog data.
Integrator Output Zero Phase
(IZ)
This phase guarantees the integrator output is at zero
volts when the AZ phase is entered so that only true system
offset voltages will be compensated for.
All internal converter timing is derived from the fre-
quency source at OSC
IN
and OSC
OUT
. This frequency
source must be either an externally provided clock signal, or
an external crystal. If an external clock is used, it must be
connected to the OSC
IN
pin and the OSC
OUT
pin must
remain floating. If a crystal is used, it must be connected
between OSC
IN
and OSC
OUT
and physically located as
close to the OSC
IN
and OSC
OUT
pins as possible. In either
case, the incoming clock frequency is divided by four and the
resulting clock serves as the internal TC530/534 timebase.
(1)
Select Integration Time
Integration time must be picked as a multiple of the
period of the line frequency. For example, t
INT
times
of 33msec, 66msec and 132msec maximize 60Hz
line rejection.
(2)
Estimate Crystal Frequency
Crystal frequencies as high as 2MHz are allowed.
Crystal frequency is estimated using:
F
IN
=
2(R)
t
INT
1
2
3
4
5
6
7
where: R
= Desired Converter Resolution
(in counts)
F
IN
= Input Frequency (in MHz)
INT = Integration Time (in seconds)
(3)
Calculate LOAD VALUE
[LOAD VALUE]
10
= 256 –
(t
INT
)(F
IN
)
1024
F
IN
can be adjusted to a standard value during this step.
The resulting base -10 LOAD VALUE must be converted to
a hexadecimal number, then loaded into the serial port prior
to initiating A/D conversion.
D
INT
and IZ Phase Timing
The duration of the D
INT
phase is a function of the
amount of voltage stored on the integrator capacitor during
INT, and the value of V
REF
. The D
INT
phase is initiated
immediately following INT and terminated when an integra-
tor output zero-crossing is detected. In general, the maxi-
mum number of counts chosen for D
INT
is twice that of INT
(with V
REF
chosen at V
IN
(max)/2).
System RESET
The TC530/534 must be forced into the AZ state when
power is first applied. A .01µF capacitor connected from
RESET to V
CC
(or external system reset logic signal) can be
used to momentarily drive RESET high for a minimum of
100msec.
Selecting Component Values for the TC530/534
(1)
Calculate Integrating Resistor (R
INT
)
The desired full-scale input voltage and amplifier
output current capability determine the value of R
INT
.
The buffer and integrator amplifiers each have a full-
scale current of 20µA.
The value of R
INT
is therefore directly calculated as
follows:
3-55
APPLICATIONS
Programming the TC530/534
AZ and INT Phase Duration:
These two phases have equal duration determined by
the crystal (or external) frequency and the timer initialization
byte (LOAD VALUE). Timing is selected as follows:
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