5V PRECISION DATA ACQUISITION
SUBSYSTEMS
TC530
TC534
Table 2. Recommend Capacitor for CINT
V
INMAX
R
INT
(MΩ) =
Value
Suggested Part Number*
20
0.1
WIMA MK12 .1/63/20
WIMA MK12 .22/63/20
WIMA MK12 .33/63/20
WIMA MK12 .47/63/20
where: VINMAX = MaximumInputVoltage(fullcount
voltage)
0.22
0.33
0.47
RINT = Integrating Resistor (in MΩ)
*WIMA Corp. listing on the last page of this data sheet.
For loop stability, RINT should be ≥ 50kΩ.
4. Calculate VREF
(2) Select Reference (CREF) and Auto Zero (CAZ)
Capacitors
The reference deintegration voltage is calculated
using:
CREF and CAZ must be low leakage capacitors (such
as polypropylene). The slower the conversion rate,
the larger the value CREF must be. Recommended
capacitors for CREF and CAZ are shown in Table 1.
Larger values for CAZ and CREF may also be used to
limit roll-over errors.
(VS – 0.9)(CINT)(RINT
)
VREF (in Volts) =
2(tINT
)
Serial Port
Communication with the TC530/534 is accomplished
over a 3 wire serial port. Data is clocked into DIN on the rising
edge of DCLK and clocked out of DOUT on the falling edge of
DCLK. R/W must be HIGH to read converted data from the
serialportandLOWtowritetheLOADVALUEtotheTC530/
534.
Table 1. CREF and CAZ Selection
Conversions Typical Value of Suggested *
Per Second
CREF, CAZ (µF) Part Number
>7
0.1
WIMA MK12 .1/63/20
2 to 7
2 or less
0.22
0.47
WIMA MK12 .22/63/20
WIMA MK12 .47/63/20
Load Value Write Cycle (Figure 4)
Following the power-up reset pulse, the LOAD VALUE
(which sets the duration of AZ and INT) must next be
transmittedtotheserialport.Toaccomplishthis,theproces-
sor monitors the state of EOC (which is available as a
hardware output or at DOUT). R/W is taken low to initiate the
write cycle only when EOC is low (during the AZ phase).
(Failure to observe EOC low may cause an offset voltage to
be developed across CINT resulting in erroneous readings).
*WIMA Corp. listing on the last page of this data sheet.
3. Calculate Integrating Capacitor (CINT
)
The integrating capacitor must be selected to maxi-
mize integrator output voltage swing. The integrator
outputvoltageswingisdefinedastheabsolutevalue
of VDD (or VSS) less 0.9V (i.e. |VDD – 0.9V| or |VSS
+
0.9V|). Using the 20µA buffer maximum output
current, the value of the integrating capacitor is
calculated using the following equation:
The 8 bit LOAD VALUE data on DIN is clocked in by DCLK
.
The processor then terminates the write cycle by taking
R/W high. (Data is transferred from the serial input shift
register to the time base counter on the rising edge of R/W,
and data conversion is initiated).
(t )(20)
INT
C
INT
(µF) =
(V – 0.9)
S
where: tINT
VS
= Integration Period
= Applied Supply Voltage
= Integrator Capacitor Value (in µF)
Data Read Cycle (Figure 5)
Dataisshiftedoutoftheserialportinthefollowingorder:
End of Conversion (EOC), Overrange (OVR), Sign (SGN),
conversion data (MSB first). When R/W is high, the state of
the EOC bit can be polled by simply reading the state of
DOUT. This allows the processor to determine if new data is
available without connecting an additional wire to the EOC
output pin (this is especially useful in a polled environment).
CINT
It is critical that the integrating capacitor have a very
low dielectric absorption. PPS capacitors are an
example of one such chemistry. Table 2 summa-
rizes various capacitors suitable for CINT
.
Input Multiplexer (TC534 Only)
A 4 input, differential multiplexer is included in the
TC534. The states of channel address lines A0 and A1
determine which differential VIN pair is routed to the con-
3-56
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