Document Number: PS-MPU-6500A-01
Revision: 1.1
Release Date: 03/05/2014
MPU-6500 Product Specification
To read the internal MPU-6500 registers, the master sends a start condition, followed by the I2C address and
a write bit, and then the register address that is going to be read. Upon receiving the ACK signal from the
MPU-6500, the master transmits a start signal followed by the slave address and read bit. As a result, the
MPU-6500 sends an ACK signal and the data. The communication ends with a not acknowledge (NACK)
signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high at the
9th clock cycle. The following figures show single and two-byte read sequences.
Single-Byte Read Sequence
Master
Slave
S
AD+W
RA
RA
S
S
AD+R
AD+R
NACK
ACK
P
ACK
ACK
ACK
ACK
ACK DATA
ACK DATA
Burst Read Sequence
Master
Slave
S
AD+W
NACK
P
DATA
6.4 I2C Terms
Signal Description
S
AD
W
Start Condition: SDA goes from high to low while SCL is high
Slave I2C address
Write bit (0)
R
Read bit (1)
ACK
Acknowledge: SDA line is low while the SCL line is high at the
9th clock cycle
NACK Not-Acknowledge: SDA line stays high at the 9th clock cycle
RA
DATA
P
MPU-6500 internal register address
Transmit or received data
Stop condition: SDA going from low to high while SCL is high
Table 15: I2C Terms
33 of 40
TDK [ TDK ELECTRONICS ]
