ICM-20602
3.5 SPI TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Units
Notes
SPI TIMING
fSPC, SPC Clock Frequency
tLOW, SPC Low Period
tHIGH, SPC High Period
tSU.CS, CS Setup Time
10
MHz
ns
1
1
1
1
1
1
1
1
1
45
45
2
ns
ns
tHD.CS, CS Hold Time
63
3
ns
tSU.SDI, SDI Setup Time
tHD.SDI, SDI Hold Time
tVD.SDO, SDO Valid Time
tDIS.SDO, SDO Output Disable Time
ns
7
ns
Cload = 20pF
40
20
ns
ns
Table 7. SPI Timing Characteristics (10 MHz Operation)
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
CS
70%
30%
tHD;CS
tSU;CS
70%
tHIGH
1/fCLK
SCLK
30%
tSU;SDI
tHD;SDI
tLOW
70%
30%
SDI
LSB IN
MSB IN
tDIS;SDO
tVD;SDO
70%
30%
SDO
MSB OUT
LSB OUT
Figure 2. SPI Bus Timing Diagram
Document Number: DS-000176
Revision: 1.0
Page 15 of 57
Revision Date: 10/03/2016
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