ICM-20602
3.4 I2C TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
Parameters
Conditions
Min
Typical
Max
Units
Notes
I2C TIMING
I2C FAST-MODE
fSCL, SCL Clock Frequency
tHD.STA, (Repeated) START Condition Hold Time
100
0.6
400
kHz
µs
1
1
tLOW, SCL Low Period
1.3
0.6
µs
µs
µs
µs
ns
ns
ns
µs
1
1
1
1
1
1
1
1
tHIGH, SCL High Period
tSU.STA, Repeated START Condition Setup Time
tHD.DAT, SDA Data Hold Time
tSU.DAT, SDA Data Setup Time
tr, SDA and SCL Rise Time
0.6
0
100
Cb bus cap. from 10 to 400 pF
Cb bus cap. from 10 to 400 pF
20+0.1Cb
20+0.1Cb
0.6
300
300
tf, SDA and SCL Fall Time
tSU.STO, STOP Condition Setup Time
tBUF, Bus Free Time Between STOP and START
Condition
1.3
µs
1
Cb, Capacitive Load for each Bus Line
tVD.DAT, Data Valid Time
< 400
pF
µs
µs
1
1
1
0.9
0.9
tVD.ACK, Data Valid Acknowledge Time
Table 6. I2C Timing Characteristics
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
tf
tSU.DAT
tr
SDA
SCL
70%
30%
70%
30%
continued below at
A
tf
tr
tVD.DAT
70%
30%
70%
30%
tHD.DAT
9th clock cycle
tHD.STA
1/fSCL
tLOW
1st clock cycle
S
tHIGH
tBUF
SDA
SCL
70%
30%
A
tSU.STO
tSU.STA
tHD.STA
tVD.ACK
70%
30%
9th clock cycle
S
P
Sr
Figure 1. I2C Bus Timing Diagram
Document Number: DS-000176
Revision: 1.0
Page 14 of 57
Revision Date: 10/03/2016
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