TSL2571
LIGHT-TO-DIGITAL CONVERTER
TAOS117A − FEBRUARY 2011
Wait Characteristics, VDD = 3 V, TA = 25ꢁ C, WEN = 1 (unless otherwise noted)
PARAMETER
Wait step size
Wait number of integration steps
TEST CONDITIONS
WTIME = 0xFF
CHANNEL
MIN
2.58
1
TYP
MAX
2.9
UNIT
ms
2.72
256
steps
AC Electrical Characteristics, VDD = 3 V, TA = 25ꢁ C (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN
0
TYP
MAX
UNIT
kHz
μs
2
f
t
Clock frequency (I C only)
400
(SCL)
(BUF)
Bus free time between start and stop condition
1.3
Hold time after (repeated) start condition. After
this period, the first clock is generated.
t
0.6
μs
(HDSTA)
t
t
t
t
t
t
t
t
Repeated start condition setup time
Stop condition setup time
Data hold time
0.6
0.6
0
μs
μs
μs
ns
μs
μs
ns
ns
pF
(SUSTA)
(SUSTO)
(HDDAT)
(SUDAT)
(LOW)
(HIGH)
F
Data setup time
100
1.3
0.6
SCL clock low period
SCL clock high period
Clock/data fall time
300
300
10
Clock/data rise time
Input pin capacitance
R
C
i
†
Specified by design and characterization; not production tested.
PARAMETER MEASUREMENT INFORMATION
t
t
(R)
t
(F)
(LOW)
V
IH
SCL
SDA
V
IL
t
t
t
(HDSTA)
(HIGH)
(SUSTA)
t
t
t
(SUSTO)
t
(BUF)
(HDDAT)
(SUDAT)
V
V
IH
IL
P
S
S
P
Stop
Condition
Start
Condition
Start
Stop
t
(LOWSEXT)
SCL
SCL
ACK
ACK
t
t
t
(LOWMEXT)
(LOWMEXT)
(LOWMEXT)
SCL
SDA
Figure 1. Timing Diagrams
Copyright E 2011, TAOS Inc.
The LUMENOLOGY r Company
r
r
www.taosinc.com
5
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
