TCS3404, TCS3414
DIGITAL COLOR SENSORS
TAOS137A − APRIL 2011
Electrical Characteristics, TA = 25ꢀ C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Power on (ADC inactive)
MIN
TYP
7.7
MAX
10
UNIT
mA
mA
μA
Power on (ADC active)
Power down
8.7
11
I
Supply current @ V = 3.6 V
DD
DD
700
1000
0.4
5
V
I
INT, SDA output low voltage
3 mA sink current
0
V
OL
Input leakage current (SDA, SCL, SYNC)
V
= V V = GND
DD, IL
−5
μA
LEAK
IH
AC Electrical Characteristics, VDD = 3.3 V, TA = 25ꢀ C (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN
0
TYP
MAX
400
UNIT
kHz
kHz
μs
2
Clock frequency 400 kHz (I C)
f
t
t
(SCL)
Clock frequency 100 kHz (SMBus)
Bus free time between start and stop condition
10
1.3
100
(BUF)
Hold time after (repeated) start condition. After
this period, the first clock is generated.
0.6
μs
(HDSTA)
t
t
t
t
t
t
t
t
t
Repeated start condition setup time
Stop condition setup time
Data hold time
0.6
0.6
0
μs
μs
μs
ns
μs
μs
ms
ns
ns
pF
μs
μs
ns
ns
(SUSTA)
(SUSTO)
(HDDAT)
(SUDAT)
(LOW)
(HIGH)
(TIMEOUT)
F
0.9
Data setup time
100
1.3
0.6
25
SCL clock low period
SCL clock high period
Detect clock/data low timeout (SMBus only)
Clock/data fall time
35
300
300
10
Clock/data rise time
R
C
Input pin capacitance
i
t
SYNC low period (see Figure 1)
SYNC high period (see Figure 1)
SYNC fall time (see Figure 1)
SYNC rise time (see Figure 1)
50
50
50
50
LOW (SYNC)
HIGH (SYNC)
F (SYNC)
t
t
t
R (SYNC)
†
Specified by design and characterization; not production tested.
t
t
t
LOW (SYNC)
R (SYNC)
F (SYNC)
t
HIGH (SYNC)
Figure 1. Timing Diagram for Sync
Copyright E 2011, TAOS Inc.
The LUMENOLOGY r Company
r
r
4
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