DS90UB913Q, DS90UB914Q
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SNLS420B –JULY 2012–REVISED APRIL 2013
Table 1. DS90UB913Q Control Registers (continued)
Addr
(Hex)
Name
Bits Field
R/W
Default
Description
Back-channel CRC Checker Enable
1:Enabled
0:Disabled
RX CRC Checker
Enable
7
6
RW
1
Forward channel Parity Generator Enable
1: Enable
0: Disable
TX Parity
Generator Enable
RW
RW
1
0
Clear CRC Error Counters.
This bit is NOT self-clearing.
1: Clear Counters
5
4
CRC Error Reset
0: Normal Operation
Automatically Acknowledge I2C Remote Write
The mode works when the system is LOCKed.
1: Enable: When enabled, I2C writes to the Deserializer
(or any remote I2C Slave, if I2C PASS ALL is enabled)
are immediately acknowledged without waiting for the
Deserializer to acknowledge the write. The accesses are
then remapped to address specified in 0x06.
0: Disable
I2C Remote Write
Auto Acknowledge
RW
0
1: Enable Forward Control Channel pass-through of all
I2C accesses to I2C Slave IDs that do not match the
Serializer I2C Slave ID. The I2C accesses are then
remapped to address specified in register 0x06.
0: Enable Forward Control Channel pass-through only of
I2C accesses to I2C Slave IDs matching either the remote
Deserializer Slave ID or the remote Slave ID.
I2C Pass-Through Mode
0: Pass-Through Disabled
1: Pass-Through Enabled
General
Configuration
0x03
3
2
1
I2C Pass All
RW
RW
RW
0
1
0
I2C
PASSTHROUGH
1:Enabled : When enabled this registers overrides the
clock to PLL mode (External Oscillator mode or Direct
PCLK mode) defined through MODE pin and allows
selection through register 0x35 in the Serializer
0: Disabled : When disabled,cClock to PLL mode
(External Oscillator mode or Direct PCLK mode) is
defined through MODE pin on the Serializer.
OV_CLK2PLL
Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the Rising Clock
0
TRFB
RW
1
Edge.
0: Parallel Interface Data is strobed on the Falling Clock
Edge.
0x04
0x05
RESERVED
7
6
RSVD
RSVD
RW
RW
0
0
Reserved
Reserved.
Allows overriding mode select bits coming from back-
channel
1: Overrides MODE select bits
0: Does not override MODE select bits
MODE_OVERRID
E
5
RW
0
Mode Select
MODE_UP To
DATE
Indicates that the status of mode select from Deserializer
is up to date
4
3
R
R
R
0
0
0
Pin_MODE_12–bit
High Frequency
1: 12 bit high frequency mode is selected.
0: 12 bit high frequency mode is not selected.
Pin_MODE_10–bit
mode
1: 10 bit mode is selected.
0: 10 bit mode is not selected.
2
1:0
RSVD
Reserved
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