C2510Fx / CC2511Fx
handle one interrupt source each time the
interrupt is triggered, hence clearing only one
module flag. When any module flag is cleared
the chip will check if there are any module
interrupt flags left that are both enabled and
asserted, if so the CPU interrupt flag will be
asserted and a new interrupt triggered.
The following code example shows how only
one module flag is handled and cleared each
time the interrupt occurs:
#pragma vector = RF_VECTOR
__interrupt void rf_interrupt (void)
{
S1CON &= ~0x03;
if(RFIF & 0x80)
// Clear CPU interrupt flag
// TX underflow
{
irq_txunf();
// Handle TX underflow
RFIF = ~0x80;
// Clear module interrupt flag
}
else if(RFIF & 0x40)
// RX overflow
{
irq_rxovf();
RFIF = ~0x40;
}
// Handle RX overflow
// Clear module interrupt flag
// Use ”else if” to check and handle other RFIF flags
}
TCON (0x88) – CPU Interrupt Flag 1
Bit
Name
Reset
R/W
R/W
H0
Description
7
0
USART1 RX interrupt flag / I2S RX interrupt flag
URX1IF /
I2SRXIF
Set to 1 when USART1 RX interrupt occurs and cleared when CPU vectors
to the interrupt service routine.
0
1
Interrupt not pending
Interrupt pending
6
5
0
0
R/W
Not used
R/W
H0
ADC interrupt flag. Set to 1 when ADC interrupt occurs and cleared when
CPU vectors to the interrupt service routine.
ADCIF
0
1
Interrupt not pending
Interrupt pending
4
3
0
0
R/W
Not used
R/W
H0
USART0 RX interrupt flag. Set to 1 when USART0 interrupt occurs and
cleared when CPU vectors to the interrupt service routine.
URX0IF
RFTXRXIF
0
1
Interrupt not pending
Interrupt pending
2
1
1
0
R/W
Reserved. Must always be set to 1.
R/W
H0
RF TX/RX complete interrupt flag. Set to 1 when RFTXRX interrupt occurs
and cleared when CPU vectors to the interrupt service routine.
0
1
Interrupt not pending
Interrupt pending
0
1
R/W
Reserved. Must always be set to 1.
SWRS055D
Page 63 of 243
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