C2510Fx / CC2511Fx
Register
Name
SFR
Address
Module
Description
Retention5
ADCCON1
ADCCON2
ADCCON3
ADCL
0xB4
0xB5
0xB6
0xBA
0xBB
0xBC
0xBD
0xB1
0xB2
0xB3
0xD1
0xD2
ADC
ADC
ADC
ADC
ADC
ADC
ADC
AES
AES
AES
DMA
DMA
DMA
DMA
DMA
DMA
DMA
FLASH
FLASH
FLASH
FLASH
FLASH
IOC
ADC Control 1
Y
Y
Y
Y
Y
Y
ADC Control 2
ADC Control 3
ADC Data Low
ADCH
ADC Data High
RNDL
Random Number Generator Data Low
RNDH
Random Number Generator Data High
Encryption/Decryption Input Data
Encryption/Decryption Output Data
Encryption/Decryption Control and Status
DMA Interrupt Flag
Y
ENCDI
N
ENCDO
ENCCS
DMAIRQ
DMA1CFGL
N
N
Y
DMA Channel 1-4 Configuration Address Low
DMA Channel 1-4 Configuration Address High
DMA Channel 0 Configuration Address Low
DMA Channel 0 Configuration Address High
DMA Channel Arm
Y
DMA1CFGH 0xD3
DMA0CFGL 0xD4
DMA0CFGH 0xD5
Y
Y
Y
DMAARM
DMAREQ
FWT
0xD6
0xD7
0xAB
0xAC
0xAD
0xAE
0xAF
0x89
0x8A
0x8B
0x8C
0x8D
0x8F
0xF1
0xF2
0xF3
0xF4
0xF5
0xF6
0xF7
0xFD
0xFE
0xFF
0xC7
Y
DMA Channel Start Request and Status
Flash Write Timing
Y
Y
FADDRL
FADDRH
FCTL
Flash Address Low
Y
Flash Address High
Y
Flash Control
[7:1]Y, [1:0]N
FWDATA
P0IFG
Flash Write Data
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Port 0 Interrupt Status Flag
Port 1 Interrupt Status Flag
Port 2 Interrupt Status Flag
Port Pins Interrupt Mask and Edge
Port 1 Interrupt Mask
P1IFG
IOC
P2IFG
IOC
PICTL
IOC
P1IEN
IOC
P0INP
IOC
Port 0 Input Mode
PERCFG
ADCCFG
P0SEL
P1SEL
P2SEL
P1INP
IOC
Peripheral I/O Control
IOC
ADC Input Configuration
Port 0 Function Select
IOC
IOC
Port 1 Function Select
IOC
Port 2 Function Select
IOC
Port 1 Input Mode
P2INP
IOC
Port 2 Input Mode
P0DIR
IOC
Port 0 Direction
P1DIR
IOC
Port 1 Direction
P2DIR
IOC
Port 2 Direction
MEMCTR
MEMORY
Memory System Control
5
Registers without retention are in their reset state after PM2 or PM3. This is only applicable for
registers / bits that are defined as R/W
SWRS055D
Page 45 of 243
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
