C2510Fx / CC2511Fx
Information Page (1 KB) which contains the
Flash Lock Bits. The lock protect bits are
written as a normal flash write to FWDATA but
the Debug Interface needs to select the Flash
Information Page first instead of the Flash
Main Page. The Information Page is selected
through the Debug Configuration which is
written through the Debug Interface only. The
Flash Controller (see Section 13.3) is used to
write and erase the contents of the flash main
memory.
11.2.3.3 Special Function Registers
The Special Function Registers (SFRs) control
several of the features of the 8051 CPU core
and/or peripherals. Many of the 8051 core
SFRs are identical to the standard 8051 SFRs.
However, there are additional SFRs that
control features that are not available in the
standard 8051. The additional SFRs are used
to interface with the peripheral units and RF
transceiver.
Table 30 shows the address to all SFRs in
CC2510Fx/CC2511Fx. The 8051 internal SFRs are
shown with grey background, while the other
SFRs are specific to CC2510Fx/CC2511Fx.
When the CPU reads instructions from flash
memory, it fetches the next instruction through
a cache. The instruction cache is provided
mainly to reduce power consumption by
reducing the amount of time the flash memory
itself is accessed. The use of the instruction
Note: All internal SFRs (shown with grey
background in Table 30, can only be accessed
through SFR memory space as these registers
are not mapped into XDATA memory space.
cache
may
be
disabled
with
the
MEMCTR.CACHDIS register bit, but doing so
will increase power consumption.
Table 31 lists the additional SFRs that are not
standard 8051 peripheral SFRs or CPU-
internal SFRs. The additional SFRs are
described in the relevant sections for each
peripheral function.
8 Bytes
80
88
90
98
P0
SP
DPL0
P1IFG
DPS
DPH0
DPL1
DPH1
U0CSR
PCON
P0INP
87
8F
97
9F
A7
AF
B7
BF
TCON
P1
P0IFG
RFIM
P2IFG
PICTL
P1IEN
MPAGE
S1CON
WOREVT0
FWT
ENDIAN
T2PR
S0CON
IEN2
T2CT
T2CTL
A0 P2
WORIRQ WORCTRL
IP0
WOREVT1
FADDRL
ADCCON1
RNDL
WORTIME0
FADDRH
ADCCON2
RNDH
WORTIME1
FCTL
A8 IEN0
B0
FWDATA
ENCDI
IP1
ENCDO
ADCL
ENCCS
ADCH
ADCCON3
SLEEP
B8 IEN1
C0 IRCON
C8
U0DBUF
WDCTL
DMAIRQ
RFD
U0BAUD
T3CNT
U0UCR
U0GCR
T3CC0
CLKCON
T3CCTL1
MEMCTR C7
T3CC1 CF
DMAREQ D7
T1CC2H DF
T1CCTL2 E7
T3CTL
T3CCTL0
D0 PSW
D8 TIMIF
E0 ACC
E8 IRCON2
DMA1CFGL DMA1CFGH DMA0CFGL DMA0CFGH DMAARM
T1CC0L
T1CNTL
T4CNT
T1CC0H
T1CNTH
T4CTL
T1CC1L
T1CTL
T1CC1H
T1CCTL0
T4CC0
T1CC2L
T1CCTL1
T4CCTL1
P1INP
RFST
RFIF
T4CCTL0
P1SEL
T4CC1
P2INP
P2DIR
EF
F7
FF
F0
B
PERCFG ADCCFG
U1DBUF U1BAUD
P0SEL
P2SEL
F8 U1CSR
U1UCR
U1GCR
P0DIR
P1DIR
Table 30: SFR Address Overview
SWRS055D
Page 44 of 243
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
