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CC2510F8RSP 参数 Datasheet PDF下载

CC2510F8RSP图片预览
型号: CC2510F8RSP
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗的SoC (系统级芯片)与MCU,存储器, 2.4 GHz射频收发器和USB控制器 [Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller]
分类和应用: 存储射频控制器
文件页数/大小: 244 页 / 2899 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
 浏览型号CC2510F8RSP的Datasheet PDF文件第219页浏览型号CC2510F8RSP的Datasheet PDF文件第220页浏览型号CC2510F8RSP的Datasheet PDF文件第221页浏览型号CC2510F8RSP的Datasheet PDF文件第222页浏览型号CC2510F8RSP的Datasheet PDF文件第224页浏览型号CC2510F8RSP的Datasheet PDF文件第225页浏览型号CC2510F8RSP的Datasheet PDF文件第226页浏览型号CC2510F8RSP的Datasheet PDF文件第227页  
C2510Fx / CC2511Fx  
0xDF17: AGCCTRL2 – AGC Control  
Bit  
Field Name  
Reset  
R/W  
Description  
Reduces the maximum allowable DVGA gain.  
7:6  
MAX_DVGA_GAIN[1:0]  
00  
R/W  
00  
01  
10  
11  
All gain settings can be used  
The highest gain setting can not be used  
The 2 highest gain settings can not be used  
The 3 highest gain settings can not be used  
5:3  
MAX_LNA_GAIN[2:0]  
000  
R/W  
Sets the maximum allowable LNA + LNA 2 gain relative to the  
maximum possible gain.  
000  
001  
010  
011  
100  
101  
110  
111  
Maximum possible LNA + LNA 2 gain  
Approx. 2.6 dB below maximum possible gain  
Approx. 6.1 dB below maximum possible gain  
Approx. 7.4 dB below maximum possible gain  
Approx. 9.2 dB below maximum possible gain  
Approx. 11.5 dB below maximum possible gain  
Approx. 14.6 dB below maximum possible gain  
Approx. 17.1 dB below maximum possible gain  
2:0  
MAGN_TARGET[2:0]  
011  
R/W  
These bits set the target value for the averaged amplitude from the  
digital channel filter (1 LSB = 0 dB).  
000  
001  
010  
011  
100  
101  
110  
111  
24 dB  
27 dB  
30 dB  
33 dB  
36 dB  
38 dB  
40 dB  
42 dB  
SWRS055D  
Page 223 of 243  
 
 
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