C2510Fx / CC2511Fx
and then the result can be read from the
I2SDATH register.
in XDATA memory space in the region 0xDF40-
0xDF48. Table 33 on Page 49 gives an
overview of register addresses while the tables
in this section describe each register. Notice
that the reset values for the registers reflect a
configuration with 16-bit stereo samples and
44.1 kHz sample rate. The I2S is not enabled at
reset.
Only one of the flags I2SCFG0.ULAWC and
I2SCFG0.ULAWE should be set to 1 when the
I2SCFG0.ENABbit is 0.
13.15.13 I2S Registers
This section describes all the registers used for
I2S control and status. The I2S registers reside
0xDF40: I2SCFG0 – I2S Configuration Register 0
Bit
Field Name
Reset
R/W
Description
Transmit interrupt enable
7
TXIEN
0
R/W
0
1
Interrupt disabled
Interrupt enabled
6
5
RXIEN
0
0
R/W
R/W
Receive interrupt enable
0
1
Interrupt disabled
Interrupt enabled
ULAWE
µ-Law expansion enable
0
1
Expansion disabled
Expansion enabled
ENAB=0
ENAB=1
Enable expansion of data to transmit
Expand data written to I2SDATH
4
ULAWC
0
R/W
µ-Law compression enable
0
1
Compression disabled
Compression enabled
ENAB=0
ENAB=1
Enable compression of data received
Compress data written to I2SDATH:I2SDATL
3
2
TXMONO
RXMONO
0
0
R/W
R/W
TX mono enable
0
1
Stereo mode
Each sample of audio data will be repeated in both channels before a new
sample is fetched. This is to enable sending a mono signal to a stereo audio sink
device.
RX mono enable
0
1
Stereo mode
Data from the right channel will be discarded, i.e. not be read into the data
registers. This feature is included because some mono devices repeat their
audio data in both channels and left is the default mono channel.
1
0
MASTER
ENAB
0
0
R/W
R/W
Master mode enable
0
Slave (CLK and WS are read from the pads)
1
Master (generate the CLK and WS)
I2S interface enable
0
1
Disable (I2S can be used as a µ-Law compression/expansion unit)
Enable
SWRS055D
Page 167 of 243
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
