C2510Fx / CC2511Fx
the watchdog timer must be cleared before
the counter expires.
Power Mode
Comments
PM1
The WDT runs but does not reset the chip upon timeout. If active mode is entered just as the timer
expires, the chip will be reset immediately, hence the WDT needs to be cleared regularly (before
timeout) also when in PM1.
PM2 and PM3
The WDT is disabled and reset, and the configuration is retained. The counter will start from 0x0000
when active mode is entered from PM2 or PM3
Table 54: Watchdog Mode and Power Modes
13.13.4 Watchdog Timer Register
WDCTL (0xC9) – Watchdog Timer Control
Bit
Name
Reset
R/W
Description
7:4
CLR[3:0] 0000
R/W
Clear timer. When 1010 followed by 0101 is written to these bits, the counter is reset to
0x0000. Note that the watchdog will only be cleared when 0101 is written within 0.5
watchdog clock period after 1010 was written. Writing to these bits when EN is 0 has no
effect.
3
EN
0
R/W
Enable timer. When a 1 is written to this bit the timer is enabled and starts
incrementing. Writing a 0 to this bit in timer mode stops the timer. Writing a 0 to this bit
in watchdog mode has no effect.
0
1
Timer disabled
Timer enabled
2
MODE
0
R/W
R/W
Mode select.
0
1
Watchdog mode
Timer mode
1:0
INT[1:0]
00
Timer interval select. These bits select the timer interval defined as a given number of
low speed oscillator periods.
Timer interval
# of periods
32.768 kHz crystal
oscillator
32 kHz RCOSC
34.667 kHz RCOSC
(calibrated,
CC2511Fx)
(calibrated, CC2510Fx
running @ 26 MHz)
00
01
10
11
32768
8192
512
1 s
1.024 s
0.256 s
16 ms
2 ms
0.945 s
0.25 s
0.236 s
15.625 ms
1.953 ms
14.769 ms
1.846 ms
64
SWRS055D
Page 151 of 243
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