C2510Fx / CC2511Fx
T4CTL (0xEB) – Timer 4 Control
Bit
Name
Reset
R/W
Description
7:5
DIV[2:0]
000
R/W
Prescaler divider value. Generates the active clock edge used to update the
counter as follows:
000
001
010
011
100
101
110
111
Tick frequency /1
Tick frequency /2
Tick frequency /4
Tick frequency /8
Tick frequency /16
Tick frequency /32
Tick frequency /64
Tick frequency /128
Note: Changes to these bits has immediate effect on the frequency of the active
clock edges.
4
3
START
OVFIM
0
1
R/W
Start timer
0
1
Suspended
Normal operation
R/W0
Overflow interrupt mask
0
1
Interrupt disabled
Interrupt enabled
2
CLR
0
R0/W1 Clear counter. Writing a 1 resets the counter to 0x00.
This bit will be 0 when returning from PM2 and PM3
1:0
MODE[1:0]
00
R/W
Timer 4 mode select. The timer operating mode is selected as follows:
00
01
10
11
Free running, repeatedly count from 0x00 to 0xFF
Down, count from T4CC0to 0x00
Modulo, repeatedly count from 0x00 to T4CC0
Up/down, repeatedly count from 0x00 to T4CC0and from T4CC0down to
0x00
SWRS055D
Page 136 of 243
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