C2510Fx / CC2511Fx
When the timer is used in Free-running Mode
or Modulo Mode the interrupt flags are set as
follows:
Timer 4. These are DMA triggers T3_CH0,
T3_CH1, T4_CH0, and T4_CH1, which are
generated on timer compare events as follows:
• T3_CH0: Timer 3 channel 0 compare
• T3_CH1: Timer 3 channel 1 compare
• T4_CH0: Timer 4 channel 0 compare
• T4_CH1: Timer 4 channel 1 compare
•
TIMIF.TxCH0IF
TIMIF.TxCH1IF are set on compare
event
and
•
TIMIF.TxOVFIF is set when counter
reaches terminal count value (overflow)
When the timer is used in Down Mode the
interrupt flags are set as follows:
13.9.7 Timer 3 and 4 Registers
This section describes the following Timer 3
and Timer 4 registers:
•
TIMIF.TxCH0IF
TIMIF.TxCH1IF are set on compare
and
event
•
•
•
T3CNT- Timer 3 Counter
T3CTL- Timer 3 Control
•
TIMIF.TxOVFIF is set when counter
reaches zero
T3CCTLn- Timer 3 Channel n Compare
Control
When the timer is used in Up/Down Mode the
interrupt flags are set as follows:
•
T3CCn - Timer 3 Channel n Compare
Value
•
TIMIF.TxCH0IF
TIMIF.TxOVFIF are set when the
and
counter turns around on zero
•
•
•
T4CNT- Timer 4 Counter
T4CTL- Timer 4 Control
•
TIMIF.TxCH1IF is set on compare
event
T4CCTLn- Timer 4 Channel n Compare
Control
In addition, the CPU interrupt flag,
IRCON.TxIFwill be asserted if the channel n
interrupt mask bit (TxCCTLn.IM) is set to 1.
•
•
T4CCn - Timer 4 Channel n Compare
Value
TIMIF- Timer 1/3/4 Interrupt Mask/Flag
13.9.6 Timer 3 and Timer 4 DMA Triggers
There are two DMA triggers associated with
Timer 3 and two DMA triggers associated with
T3CNT (0xCA) – Timer 3 Counter
Bit
Name
Reset
R/W
Description
Timer count byte. Contains the current value of the 8-bit counter
7:0
CNT[7:0]
0x00
R
SWRS055D
Page 132 of 243
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