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CC2510F8RSP 参数 Datasheet PDF下载

CC2510F8RSP图片预览
型号: CC2510F8RSP
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗的SoC (系统级芯片)与MCU,存储器, 2.4 GHz射频收发器和USB控制器 [Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller]
分类和应用: 存储射频控制器
文件页数/大小: 244 页 / 2899 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
 浏览型号CC2510F8RSP的Datasheet PDF文件第97页浏览型号CC2510F8RSP的Datasheet PDF文件第98页浏览型号CC2510F8RSP的Datasheet PDF文件第99页浏览型号CC2510F8RSP的Datasheet PDF文件第100页浏览型号CC2510F8RSP的Datasheet PDF文件第102页浏览型号CC2510F8RSP的Datasheet PDF文件第103页浏览型号CC2510F8RSP的Datasheet PDF文件第104页浏览型号CC2510F8RSP的Datasheet PDF文件第105页  
C2510Fx / CC2511Fx  
13.5.2 DMA Configuration Parameters  
Variable Length Transfers: When VLEN000  
and VLEN111, the DMA channel will use the  
first byte or word (for word, bits 12:0 are used)  
in source data as the transfer count, hence  
allowing variable length transfers. When using  
variable length transfer, various options  
regarding how to count number of bytes to  
transfer is given.  
Setup and control of the DMA operation is  
performed by the user software. This section  
describes the parameters which must be  
configured before a DMA channel can be  
used. Section 13.5.3 on Page 103 describes  
how the parameters are set up in software and  
passed to the DMA controller.  
Options are:  
The behavior of each of the five DMA  
channels is configured with the following  
parameters:  
1. Default: Transfer number of bytes/words  
commanded by first byte/word + 1  
(transfers length byte/word, and then as  
many bytes/words as dictated by length  
byte/word)  
13.5.2.1 Source Address (SRCADDR)  
The address of the location in XDATA memory  
space where the DMA channel shall start to  
read data for the transfer.  
2. Transfer  
number  
of  
bytes/words  
commanded by first byte/word (transfers  
length byte/word, and then as many  
bytes/words as dictated by length  
byte/word - 1)  
13.5.2.2 Destination Address (DESTADDR)  
3. Transfer  
number  
of  
bytes/words  
The address of the location in XDATA memory  
space where the DMA channel will write the  
data read from the source address. The user  
must ensure that the destination is writable.  
commanded by first byte/word + 2  
(transfers length byte/word, and then as  
many bytes/words as dictated by length  
byte/word + 1)  
4. Transfer  
number  
of  
bytes/words  
13.5.2.3 Transfer Count  
commanded by first byte/word + 3  
(transfers length byte/word, and then as  
many bytes/words as dictated by length  
byte/word + 2)  
The number of bytes/words needed to be  
transferred for the DMA transfer to be  
complete. When the transfer count is reached,  
the DMA controller rearms or disarms the  
DMA channel (depending on transfer mode)  
and alert the CPU by setting the  
DMAIRQ.DMAIFn bit to 1. If IRQMASK=1,  
IRCON.DMAIFwill also be set and an interrupt  
request is generated if IEN1.DMAIE=1. The  
transfer count can be of fixed or variable  
length depending on how the DMA channel is  
configured.  
In any case, the LEN setting is used as  
maximum transfer count. LEN should be set to  
the largest allowed transfer count (specified by  
the first byte or word) plus one.  
Note that the M8 bit is only used when byte  
size transfers are chosen.  
Figure 26 shows the different VLENoptions.  
Fixed Length Transfers: When VLEN=000or  
VLEN=111, the length is set by the LENsetting  
SWRS055D  
Page 101 of 243  
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