C2510Fx / CC2511Fx
Byte/Word n+3
Byte/Word n+2
Byte/Word n+1
Byte/Word n
Byte/Word n+3
Byte/Word n+2
Byte/Word n+1
Byte/Word n
Byte/Word n+3
Byte/Word n+3
Byte/Word n+2
Byte/Word n+1
Byte/Word n
Byte/Word n+2
Byte/Word n+1
Byte/Word n
Byte/Word n-1
Byte/Word n-2
Byte/Word n-1
Byte/Word n-2
Byte/Word n-1
Byte/Word n-2
Byte/Word n-1
Byte/Word n-2
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Byte/Word 3
Byte/Word 2
Byte/Word 1
Length = n
Byte/Word 3
Byte/Word 2
Byte/Word 1
Length = n
Byte/Word 3
Byte/Word 2
Byte/Word 1
Length = n
Byte/Word 3
Byte/Word 2
Byte/Word 1
Length = n
VLEN = 001
VLEN = 010
VLEN = 011
VLEN = 100
If LEN ≤ n, LEN bytes/words are
being transferred. The dotted line
shows the case where LEN = n
Figure 26: Variable Length (VLEN) Transfer Options
which
the
CPU
is
notified
13.5.2.4 Byte or Word Transfers (WORDSIZE)
(DMAIRQ.DMAIFn=1) and the DMA channel is
rearmed.
Determines whether each DMA transfer
should be 8-bit (byte) or 16-bit (word).
13.5.2.6 Trigger Event (TRIG)
13.5.2.5 DMA Transfer Mode (TMODE)
All DMA transfers are initiated by so-called
DMA trigger events, which either starts a DMA
block transfer or a single DMA transfer (or
repeated versions of these). Each DMA
channel can be set up to sense on a single
trigger. The TRIG field in the configuration
determines which trigger the DMA channel is
to use. In addition to the configured trigger, a
DMA channel can always be triggered by
setting its designated DMAREQ.DMAREQn flag.
The DMA trigger sources are described in
Table 51 on Page 105.
The transfer mode determines how the DMA
channel behaves when transferring data.
There are four different transfer modes.
Single. On a trigger a single DMA transfer
occurs and the DMA channel awaits the next
trigger. After completing the number of
transfers specified by the transfer count, the
CPU is notified (DMAIRQ.DMAIFn=1) and the
DMA channel is disarmed.
Block. On a trigger the number of DMA
transfers specified by the transfer count is
performed as quickly as possible, after which
the CPU is notified (DMAIRQ.DMAIFn=1) and
the DMA channel is disarmed.
13.5.2.7 Source and Destination Increment
(SRCINCand DESTINC)
Repeated single. On a trigger a single DMA
transfer occurs and the DMA channel awaits
the next trigger. After completing the number
of transfers specified by the transfer count, the
CPU is notified (DMAIRQ.DMAIFn=1) and the
DMA channel is rearmed.
When the DMA channel is armed or rearmed,
the source and destination addresses are
transferred to internal address pointers. These
pointers, and hence the source and
destination addresses, can be controlled to
increment, decrement, or not change between
transfers in order to give good flexibility. The
possibilities for address increment/decrement
are:
Repeated block. On a trigger the number of
DMA transfers specified by the transfer count
is performed as quickly as possible, after
SWRS055D
Page 102 of 243
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