CC2430
8051 CPU : Interrupts
IEN1 (0xB8) – Interrupt Enable 1
Bit
7:6
5
Name
-
Reset
00
R/W
R0
Description
Not used. Read as 0
P0IE
0
R/W
P0IE – Port 0 interrupt enable
0
1
Interrupt disabled
Interrupt enabled
T4IE
T3IE
T2IE
T1IE
DMAIE
4
3
2
1
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
T4IE - Timer 4 interrupt enable
0
1
Interrupt disabled
Interrupt enabled
T3IE - Timer 3 interrupt enable
0
1
Interrupt disabled
Interrupt enabled
T2IE – Timer 2 interrupt enable
0
1
Interrupt disabled
Interrupt enabled
T1IE – Timer 1 interrupt enable
0
1
Interrupt disabled
Interrupt enabled
DMAIE – DMA transfer interrupt enable
0
1
Interrupt disabled
Interrupt enabled
IEN2 (0x9A) – Interrupt Enable 2
Bit
7:6
5
Name
-
Reset
00
R/W
R0
Description
Not used. Read as 0
WDTIE
0
R/W
WDTIE – Watchdog timer interrupt enable
0
1
Interrupt disabled
Interrupt enabled
P1IE
4
3
2
1
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
P1IE– Port 1 interrupt enable
0
1
Interrupt disabled
Interrupt enabled
UTX1IE
UTX0IE
P2IE
UTX1IE – USART1 TX interrupt enable
0
1
Interrupt disabled
Interrupt enabled
UTX0IE - USART0 TX interrupt enable
0
1
Interrupt disabled
Interrupt enabled
P2IE – Port 2 interrupt enable
0
1
Interrupt disabled
Interrupt enabled
RFIE
RFIE – RF general interrupt enable
0
1
Interrupt disabled
Interrupt enabled
CC2430 revision E Data Sheet (rev. 2.1) SWRS036F
Page 53 of 211