CC2430
8051 CPU : Interrupts
IEN0 (0xA8) – Interrupt Enable 0
Bit
Name
Reset
R/W
Description
EA
7
0
R/W
Disables all interrupts.
0
1
No interrupt will be acknowledged
Each interrupt source is individually enabled or disabled by
setting its corresponding enable bit
-
6
5
0
0
R0
Not used. Read as 0
STIE
R/W
STIE – Sleep Timer interrupt enable
0
1
Interrupt disabled
Interrupt enabled
ENCIE
4
3
2
1
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
ENCIE – AES encryption/decryption interrupt enable
0
1
Interrupt disabled
Interrupt enabled
URX1IE
URX0IE
ADCIE
URX1IE – USART1 RX interrupt enable
0
1
Interrupt disabled
Interrupt enabled
URX0IE - USART0 RX interrupt enable
0
1
Interrupt disabled
Interrupt enabled
ADCIE – ADC interrupt enable
0
1
Interrupt disabled
Interrupt enabled
RFERRIE
RFERRIE – RF TX/RX FIFO interrupt enable
0
1
Interrupt disabled
Interrupt enabled
CC2430 revision E Data Sheet (rev. 2.1) SWRS036F
Page 52 of 211
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