CC2430
8051 CPU
interrupts missing this they are to be treated
as level triggered (apply to ports P0, P1 and
P2). The switchboxes are shown in default
: Interrupts
pulsed or edge shaped interrupt sources one
should clear CPU interrupt flag registers prior
to clearing source flag bit, if available, for flags
that are not automatically cleared. For level
sources one has to clear source prior to
clearing CPU flag.
state, and
or
indicates rising or falling
edge detection, i.e. at what time instance the
interrupt is generated. As a general rule for
Table 30: Interrupts Overview
Interrupt
number
Description
Interrupt
name
Interrupt
Vector
Interrupt Mask,
CPU
Interrupt Flag,
CPU
0
RF TX FIFO underflow and RX
FIFO overflow.
TCON.RFERRIF7
IEN0.RFERRIE
RFERR
03h
TCON.ADCIF7
TCON.URX0IF7
TCON.URX1IF7
S0CON.ENCIF
IEN0.ADCIE
IEN0.URX0IE
IEN0.URX1IE
IEN0.ENCIE
1
2
3
4
ADC end of conversion
USART0 RX complete
USART1 RX complete
ADC
0Bh
13h
1Bh
23h
URX0
URX1
ENC
AES encryption/decryption
complete
IEN0.STIE
IEN2.P2IE
IEN2.UTX0IE
IEN1.DMAIE
IEN1.T1IE
IRCON.STIF
5
6
7
8
9
Sleep Timer compare
Port 2 inputs
ST
2Bh
33h
3Bh
43h
4Bh
IRCON2.P2IF8
IRCON2.UTX0IF
IRCON.DMAIF
IRCON.T1IF7,8
P2INT
UTX0
DMA
T1
USART0 TX complete
DMA transfer complete
Timer 1 (16-bit)
capture/compare/overflow
IRCON.T2IF7,8
IRCON.T3IF7,8
IRCON.T4IF7,8
IRCON.P0IF8
IRCON2.UTX1IF
IRCON2.P1IF8
S1CON.RFIF8
IRCON2.WDTIF
IEN1.T2IE
IEN1.T3IE
IEN1.T4IE
IEN1.P0IE
IEN2.UTX1IE
IEN2.P1IE
IEN2.RFIE
IEN2.WDTIE
10
11
12
13
14
15
16
17
Timer 2 (MAC Timer)
T2
53h
5Bh
63h
6Bh
73h
7Bh
83h
8Bh
Timer 3 (8-bit) compare/overflow
Timer 4 (8-bit) compare/overflow
Port 0 inputs
T3
T4
P0INT
UTX1
P1INT
RF
USART1 TX complete
Port 1 inputs
RF general interrupts
Watchdog overflow in timer mode
WDT
7 HW cleared when Interrupt Service Routine is called.
8 Additional IRQ mask and IRQ flag bits exists.
CC2430 revision E Data Sheet (rev. 2.1) SWRS036F
Page 50 of 211
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