CC2430
Radio : Radio Registers
FSCTRLH (0xDF10)
Bit
Name
Reset
R/W
Description
Number of consecutive reference clock periods with
successful sync windows required to indicate lock:
7:6
LOCK_THR[1:0]
01
R/W
00 : 64
01 : 128
10 : 256
11 : 512
Frequency synthesizer calibration done.
5
CAL_DONE
0
R
0 : Calibration not performed since the last time the FS was
turned on.
1 : Calibration performed since the last time the FS was
turned on.
Calibration status, '1' when calibration in progress.
4
3
CAL_RUNNING
LOCK_LENGTH
0
0
R
LOCK_WINDOW pulse width:
0: 2 CLK_PRE periods
R/W
1: 4 CLK_PRE periods
PLL lock status
2
LOCK_STATUS
FREQ[9:8]
0
R
0 : PLL is not in lock
1 : PLL is in lock
Frequency control word. Used directly in TX, in RX the LO
frequency is automatically set 2 MHz below the RF
frequency.
1:0
01
R/W
(2405
MHz)
2048 + FREQ
[9 : 0
]
Frequency division =
⇔
4
fRF
fLO
=
=
(
2048 + FREQ
[
9 : 0
]
)
MHz
(
2048 + FREQ
[9 : 0
]
− 2⋅ RXEN MHz
)
FSCTRLL (0xDF11)
Bit
Name
Reset
R/W
Description
Frequency control word. Used directly in TX, in RX the LO
frequency is automatically set 2 MHz below the RF
frequency.
7:0
FREQ[7:0]
0x65
R/W
(2405
MHz)
2048 + FREQ
[
9 : 0
]
⇔
Frequency division =
4
fRF
fLO
=
=
(
2048 + FREQ
[
9 : 0
]
)
MHz
(
2048 + FREQ
[9 : 0
]
− 2⋅ RXEN MHz
)
CSPT (0xDF16)
Bit
Name
Reset
R/W
Description
CSP T Data register. Contents is decremented each time
MAC Timer overflows while CSP program is running. CSP
program stops when is about to count to 0. Setting T=0xFF
disables decrement function.
7:0
CSPT
0x00
R/W
CSPX (0xDF12)
Bit
Name
Reset
R/W
Description
CSP X Data register. Used by CSP WAITX, RANDXY and
conditional instructions
7:0
CSPX
0x00
R/W
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 192 of 211
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
