CC2430
Radio : CSMA/CA Strobe Processor
14.34.2 Data Registers
decremented by 1 each time the MAC timer
overflows. When CSPTreaches zero, program
execution is halted and the interrupt
IRQ_CSP_STOP is asserted. The CSPT
register will not be decremented if the CPU
writes 0xFF to this register.
The CSP has three data registers CSPT, CSPX,
CSPY and CSPZ, which are read/write
accessible for the CPU as RF registers. These
registers are read or modified by some
instructions, thus allowing the CPU to set
parameters to be used by a CSP program or
allowing the CPU to read CSP program status.
Note: If the CSPT register compare function is
not used, this register must be set to 0xFF
before the program execution is started.
The CSPTdata register is not modified by any
instruction. The CSPT data register is used to
set a MAC Timer overflow compare value.
Once program execution has started on the
CSP, the content of this register is
14.34.3 Program Execution
After the instruction memory has been filled,
program execution is started by writing the
immediate command strobe instruction
ISSTART to the RFST register. The program
execution will continue until either the
instruction at last location has been executed,
the CSPT data register contents is zero, a
SSTOP instruction has been executed, an
immediate ISSTOP instruction is written to
RFST or until a SKIP instruction returns a
location beyond the last location in the
instruction memory. The CSP runs at 8 MHz
clock frequency.
Immediate Command Strobe instructions may
be written to RFST while a program is being
executed. In this case the Immediate
instruction will bypass the instruction in the
instruction memory, which will be completed
once the Immediate instruction has been
completed.
During program execution, reading RFST will
return the current instruction being executed.
An exception to this is the execution of
immediate command strobes, during which
RFSTwill return C0h.
14.34.4 Interrupt Requests
The CSP has three interrupts flags which can
produce the RF interrupt vector. These are the
following:
•
•
IRQ_CSP_WT:
asserted
when
the
processor continues executing the next
instruction after a WAIT W or WAITX
instruction.
IRQ_CSP_INT:
processor executes an INT instruction.
•
IRQ_CSP_STOP: asserted when the
processor has executed the last instruction
in memory and when the processor stops
due to a SSTOP or ISSTOP instruction or
CSPTregister equal zero.
asserted
when the
14.34.5 Random Number Instruction
There will be a delay in the update of the
random number used by the RANDXY
instruction. Therefore if an instruction,
RANDXY, that uses this value is issued
immediately after
instruction, the random value read may be the
same in both cases.
a
previous RANDXY
14.34.6 Running CSP Programs
The basic flow for loading and running a
program on the CSP is shown in Figure 50.
by the SSTOP or ISTOP instruction, the
program memory will be cleared. It is also
importat to note that a WAIT W or WEVENT
instruction can not be executed between X
register update and X data read by one of the
following instructions: RPT, SKIP or WAITX. If
this is done the CSPX register will be
decremented on each MAC timer (Timer2)
overflow occurrence.
When program execution stops due to end of
program the current program remains in
program memory. This makes it possible to
run the same program again by starting
execution with the ISSTART command.
However, when program execution is stopped
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 177 of 211
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