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CC2430F32RTC 参数 Datasheet PDF下载

CC2430F32RTC图片预览
型号: CC2430F32RTC
PDF下载: 下载PDF文件 查看货源
内容描述: 真正的系统级芯片解决方案的2.4 GHz IEEE 802.15.4 / ZigBee的 [A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee]
分类和应用: 电信集成电路
文件页数/大小: 212 页 / 1862 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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CC2430  
Peripherals : 16-bit timer, Timer1  
13.6.11 Timer 1 Registers  
This section describes the Timer 1 registers  
which consist of the following registers:  
T1CCxL– Timer 1 Channel x  
Capture/Compare Value Low  
T1CNTH– Timer 1 Count High  
T1CNTL– Timer 1 Count Low  
T1CTL– Timer 1 Control and Status  
T1CCTLx– Timer 1 Channel x  
Capture/Compare Control  
The TIMIF.OVFIM register bit resides in the  
TIMIF register, which is described together  
with Timer 3 and Timer 4 registers on page  
118.  
T1CCxH– Timer 1 Channel x  
Capture/Compare Value High  
T1CNTH (0xE3) – Timer 1 Counter High  
Bit  
Name  
Reset  
R/W  
Description  
7:0  
0x00  
R
Timer count high order byte. Contains the high byte of the 16-bit  
timer counter buffered at the time T1CNTL is read.  
CNT[15:8]  
T1CNTL (0xE2) – Timer 1 Counter Low  
Bit  
Name  
Reset  
R/W  
Description  
7:0  
0x00  
R/W  
Timer count low order byte. Contains the low byte of the 16-bit  
timer counter. Writing anything to this register results in the  
counter being cleared to 0x0000.  
CNT[7:0]  
T1CTL (0xE4) – Timer 1 Control and Status  
Bit  
Name  
Reset  
R/W  
Description  
7
0
R/W0  
Timer 1 channel 2 interrupt flag. Set when the channel 2 interrupt  
condition occurs. Writing a 1 has no effect.  
CH2IF  
6
5
4
0
0
0
R/W0  
R/W0  
R/W0  
Timer 1 channel 1 interrupt flag. Set when the channel 1 interrupt  
condition occurs. Writing a 1 has no effect.  
CH1IF  
CH0IF  
OVFIF  
Timer 1 channel 0 interrupt flag. Set when the channel 0 interrupt  
condition occurs. Writing a 1 has no effect.  
Timer 1 counter overflow interrupt flag. Set when the counter  
reaches the terminal count value in free-running or modulo mode,  
and when zero is reached counting down in up-down mode.  
Writing a 1 has no effect.  
3:2  
00  
R/W  
Prescaler divider value. Generates the active clock edge used to  
update the counter as follows:  
DIV[1:0]  
00  
01  
10  
11  
Tick frequency/1  
Tick frequency/8  
Tick frequency/32  
Tick frequency/128  
1:0  
00  
R/W  
Timer 1 mode select. The timer operating mode is selected as  
follows:  
MODE[1:0]  
00  
01  
10  
Operation is suspended  
Free-running, repeatedly count from 0x0000 to 0xFFFF  
Modulo, repeatedly count from 0x0000 to T1CC0  
11  
Up/down, repeatedly count from 0x0000 to T1CC0and  
from T1CC0down to 0x0000  
CC2430 Data Sheet (rev. 2.1) SWRS036F  
Page 106 of 211  
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