CC2430
Peripherals : Flash Controller
Figure 16: Performing CPU Flash write
13.3.3
Flash Page Erase
After a flash page erase, all bytes in the
erased page are set to 1.
Performing flash erase from flash memory
The steps required to perform a flash page
erase from within flash memory are outlined in
Figure 17.
A
page erase is initiated by setting
FCTL.ERASE to 1. The page addressed by
FADDRH[6:1]is erased when a page erase is
initiated. Note that if a page erase is initiated
Note that, while executing program code from
within flash memory, when a flash erase or
write operation is initiated, program execution
will resume from the next instruction when the
flash controller has completed the operation.
The flash erase operation requires that the
instruction that starts the erase i.e. writing to
FCTL.ERASEis followed by a NOP instruction
as shown in the example code. Omitting the
NOP instruction after the flash erase operation
will lead to undefined behavior.
simultaneously with
a
page write, i.e.
FCTL.WRITE is set to 1, the page erase will
be performed before the page write operation.
The FCTL.BUSYbit can be polled to see when
the page erase has completed.
Note: If flash page erase operation is
performed from within flash memory and the
watchdog timer is enabled, a watchdog timer
interval must be selected that is longer than 20
ms, the duration of the flash page erase
operation, so that the CPU will manage to
clear the watchdog timer.
; Erase page in flash memory
; Assumes 32 MHz system clock is used
;
CLR
MOV
JB
MOV
MOV
MOV
NOP
RET
EA
A,FCTL
ACC.7,C1
FADDRH,#00h
FWT,#2Ah
FCTL,#01h
;mask interrupts
;wait until flash controller is ready
C1:
;setup flash address high
;setup flash timing
;erase page
;must always execute a NOP after erase
;continues here when flash is ready
Figure 17: Flash page erase performed from flash memory
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 75 of 211
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