CC2430
8051 CPU : Instruction Set Summary
11.3.6
Stack Pointer
The stack resides in DATA memory space and
grows upwards. The PUSH instruction first
increments the Stack Pointer (SP) and then
copies the byte into the stack. The Stack
Pointer is initialized to 0x07 after a reset and it
is incremented once to start from location 0x08
which is the first register (R0) of the second
register bank. Thus, in order to use more than
one register bank, the SP should be initialized
to a different location not used for data
storage.
SP (0x81) – Stack Pointer
Bit
Name
Reset
R/W
Description
Stack Pointer
7:0
0x07
R/W
SP[7:0]
11.4 Instruction Set Summary
The 8051 instruction set is summarized in
Table 28. All mnemonics copyrighted © Intel
Corporation, 1980.
•
•
•
addr11 – 11-bit destination address. Used
by ACALL and AJMP. The branch will be
within the same 2 KB page of program
memory as the first byte of the following
instruction.
rel – Signed (two’s complement) 8-bit
offset byte. Used by SJMP and all
conditional jumps. Range is –128 to +127
bytes relative to first byte of the following
instruction.
The following conventions are used in the
instruction set summary:
•
•
Rn – Register R7-R0 of the currently
selected register bank.
direct – 8-bit internal data location’s
address. This can be DATA area (0x00 –
0x7F) or SFR area (0x80 – 0xFF).
@Ri – 8-bit internal data location, DATA
area (0x00 – 0xFF) addressed indirectly
through register R1or R0.
bit – direct addressed bit in DATA area or
SFR.
•
The instructions that affect CPU flag settings
located in PSW are listed in Table 29 on page
49. Note that operations on the PSWregister or
bits in PSWwill also affect the flag settings.
•
•
•
#data
instruction.
–
8-bit constant included in
#data16 – 16-bit constant included in
instruction.
addr16 – 16-bit destination address. Used
by LCALL and LJMP. A branch can be
anywhere within the 64 KB CODE memory
space.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 44 of 211
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