CC2430
8051 CPU : CPU Registers
11.3 CPU Registers
This section describes the internal registers
found in the CPU.
11.3.1
Data Pointers
execution of an instruction that uses the data
pointer, e.g. in one of the above instructions.
The CC2430 has two data pointers, DPTR0
and DPTR1 to accelerate the movement of
data blocks to/from memory. The data pointers
are generally used to access CODE or XDATA
space e.g.
The data pointers are two bytes wide
consisting of the following SFRs:
•
•
DPTR0 – DPH0:DPL0
DPTR1 – DPH1:DPL1
MOVC A,@A+DPTR
MOV A,@DPTR
.
The data pointer select bit, bit 0 in the Data
Pointer Select register DPS, chooses which
data pointer shall be the active one during
DPH0 (0x83) – Data Pointer 0 High Byte
Bit
Name
Reset
R/W
Description
7:0
0
R/W
Data pointer 0, high byte
DPH0[7:0]
DPL0 (0x82) – Data Pointer 0 Low Byte
Bit
Name
Reset
R/W
Description
7:0
0
R/W
Data pointer 0, low byte
DPL0[7:0]
DPH1 (0x85) – Data Pointer 1 High Byte
Bit
Name
Reset
R/W
Description
7:0
0
R/W
Data pointer 1, high byte
DPH1[7:0]
DPL1 (0x84) – Data Pointer 1 Low Byte
Bit
Name
Reset
R/W
Description
7:0
0
R/W
Data pointer 1, low byte
DPL1[7:0]
DPS (0x92) – Data Pointer Select
Bit
Name
-
Reset
R/W
Description
7:1
0x00
R0
Not used
0
0
R/W
Data pointer select. Selects active data pointer.
DPS
0 : DPTR0
1 : DPTR1
11.3.2
Registers R0-R7
0x0F, 0x10-0x17 and 0x18-0x1F (XDATA
address range 0xFF00 to 0xFF1F). Each
register bank contains the eight 8-bit register
R0-R7. The register bank to be used is
selected through the Program Status Word
PSW.RS[1:0].
The CC2430 provides four register banks (not
to be confused with CODE memory space
banks that only applies to flash memory
organization) of eight registers each. These
register banks are mapped in the DATA
memory space at addresses 0x00-0x07, 0x08-
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 42 of 211
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