CC1110Fx / CC1111Fx
be transferred. This bit will be cleared by
HW when the data packet has been
sent)
generated (if enabled properly). EP0 will then
switch to the IDLE state. Firmware should then
set the USBCS0.CLR_SETUP_ENDbit to 1 and
• An IN transaction has been completed
(the interrupt is generated during the
Status stage of the transaction)
abort
the
current
transfer.
If
USBCS0.OUTPKT_RDY is asserted, this
indicates that another Setup Packet has been
received that firmware should process.
• A
STALL
has
been
sent
(USBCS0.SENT_STALL=1)
13.16.5.2 SETUP Transactions (IDLE State)
• A control transfer ends due to a
premature end of control transfer
(USBCS0.SETUP_END=1)
The control transfer consists of 2 – 3 stages of
transactions (Setup – Data - Status or Setup -
Status). The first transaction is a Setup
transaction. A successful Setup transaction
comprises three sequential packets (a token
packet, a data packet, and a handshake
packet), where the data field (payload) of the
data packet is exactly 8 bytes long and are
referred to as the Setup Packet. In the Setup
stage of a control transfer, EP0 will be in the
IDLE state. The USB controller will reject the
data packet if the Setup Packet is not 8 bytes.
Also, the USB controller will examine the
contents of the Setup Packet to determine
whether or not there is a Data stage in the
control transfer. If there is a Data stage, EP0
will switch state to TX (IN transaction) or RX
Any of these events will cause the
USBIIF.EP0IF to be asserted regardless of
the status of the EP0 interrupt mask bit
USBIIE.EP0IE. If the EP0 interrupt mask bit
is set to 1, the CPU interrupt flag
IRCON2.USBIF will also be asserted. An
interrupt request is only generated if
IEN2.USBIE and USBIIE.EP0IE are both
set to 1.
13.16.5.1 Error Conditions
When a protocol error occurs, the USB
controller sends a STALL handshake. The
USBCS0.SENT_STALL bit is asserted and an
interrupt request is generated if the endpoint 0
interrupt is properly enabled. A protocol error
can be any of the following:
(OUT
transaction)
when
the
USBCS0.CLR_OUTPKT_RDY bit is set to 1 (if
USBCS0.DATA_END=0).
• An OUT token is received after
USBCS0.DATA_END has been set to
complete the OUT Data stage (the host
tries to send more data than expected)
• An IN token is received after
USBCS0.DATA_END has been set to
complete the IN Data stage (the host
tries to receive more data than
expected)
• The USB host tries to send a packet that
exceeds the maximum packet size
during the OUT Data stage
• The size of the DATA1 packet received
during the Status stage is not 0
When
a
packet
is
received,
the
USBCS0.OUTPKT_RDYbit will be asserted and
an interrupt request is generated (EP0
interrupt) if the interrupt has been enabled.
Firmware should perform the following when a
Setup Packet has been received:
1. Unload the Setup Packet from the EP0
FIFO
2. Examine the contents and perform the
appropriate operations
3. Set the USBCS0.CLR_OUTPKT_RDY bit
to 1. This denotes the end of the Setup
stage. If the control transfer has no Data
stage, the USBCS0.DATA_END bit must
also be set. If there is no Data stage, the
USB Controller will stay in the IDLE
state.
The firmware can also terminate the current
transaction
by
setting
the
USBCS0.SEND_STALL bit to 1. The USB
controller will then send a STALL handshake in
response to the next requests from the USB
host.
13.16.5.3 IN Transactions (TX state)
If the control transfer requires data to be sent
to the host, the Setup stage will be followed by
one or more IN transactions in the Data stage.
In this case the USB controller will be in TX
state and only accept IN tokens. A successful
IN transaction comprises two or three
sequential packets (a token packet, a data
If an EP0 interrupt is caused by the assertion
of the USBCS0.SENT_STALL bit, this bit
should be de-asserted and firmware should
consider the transfer as aborted (free memory
buffers etc.).
If EP0 receives an unexpected token during
the Data stage, the USBCS0.SETUP_END bit
will be asserted and an EP0 interrupt will be
SWRS033E
Page 171 of 239
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