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CC1110FX 参数 Datasheet PDF下载

CC1110FX图片预览
型号: CC1110FX
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗低于1 GHz的射频系统级芯片(SoC )与MCU,存储器,收发器和USB控制器 [Low-power sub-1 GHz RF System-on-Chip (SoC) with MCU, memory, transceiver, and USB controller]
分类和应用: 存储射频控制器
文件页数/大小: 240 页 / 2823 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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CC1110Fx / CC1111Fx  
13.14 USART  
USART0 and  
communications interfaces that can be  
operated separately in either asynchronous  
UART mode or in synchronous SPI mode. The  
two USARTs are identical in functionality but  
are assigned to separate I/O pins. Refer to  
section 13.4 on page 91 for I/O configuration.  
USART1  
are  
serial  
transmit data, and an interrupt request is  
generated if IEN2.UTXxIE=1. This happens  
immediately after the transmission has been  
started, hence a new data byte value can be  
loaded into the data buffer while the byte is  
being transmitted.  
13.14.1.2 UART Receive  
13.14.1 UART Mode  
Data reception on the UART is initiated when a  
1 is written to the UxCSR.RE bit. The UART  
will then search for a valid start bit on the  
RXDx input pin and set the UxCSR.ACTIVEbit  
high. When a valid start bit has been detected  
the received byte is shifted into the receive  
register. The UxCSR.RX_BYTE bit and the  
CPU interrupt flag, TCON.URXxIF, is set to 1  
when the operation has completed and an  
For asynchronous serial interfaces, the UART  
mode is provided. In UART mode the interface  
uses  
a
two-wire or four-wire interface  
consisting of the pins RXD and TXD, and  
optionally RTS and CTS. The UART mode  
includes the following features:  
8 or 9 data bits  
Odd, even, or no parity  
interrupt  
IEN0.URXxIE=1.  
UxCSR.ACTIVE will go low.  
request  
is  
generated  
same  
if  
time  
Configurable start and stop bit level  
Configurable LSB or MSB first transfer  
Independent receive and transmit  
interrupts  
Independent receive and transmit DMA  
triggers  
At  
the  
The received data byte is available through the  
UxDBUF register. When UxDBUF is read,  
UxCSR.RX_BYTE is cleared by hardware.  
Parity and framing error status  
13.14.1.3 UART Hardware Flow Control  
The UART mode provides full duplex  
asynchronous  
transfers  
and  
the  
Hardware flow control is enabled when the  
UxUCR.FLOW bit is set to 1. The RTS output  
will then be driven low when the receive  
register is empty and reception is enabled.  
Transmission of a byte will not occur before  
the CTS input go low.  
synchronization of bits in the receiver does not  
interfere with the transmit function. A UART  
byte transfer consists of a start bit, eight data  
bits, an optional ninth data or parity bit, and  
one or two stop bits. Note that the data  
transferred is referred to as a byte, although  
the data can actually consist of eight or nine  
bits.  
13.14.1.4 UART Character Format  
If the BIT9and PARITYbits in register UxUCR  
are set high, parity generation and detection is  
enabled. The parity is computed and  
transmitted as the ninth bit, and during  
reception, the parity is computed and  
compared to the received ninth bit. If there is a  
parity error, the UxCSR.ERR bit is set high.  
This bit is cleared when UxCSRis read.  
The UART operation is controlled by the  
USART x Control and Status registers, UxCSR,  
and the USART x UART Control register,  
UxUCR, where x is the USART number, 0 or 1.  
The UART mode is selected when  
UxCSR.MODEis set to 1.  
13.14.1.1 UART Transmit  
The number of stop bits to be transmitted is set  
to one or two bits determined by the register bit  
UxUCR.SPB. The receiver will always check for  
one stop bit. If the first stop bit received during  
reception is not at the expected stop bit level, a  
framing error is signaled by setting register bit  
UxCSR.FE high. UxCSR.FE is cleared when  
UxCSR is read. The receiver will check both  
stop bits when UxUCR.SPB=1. Note that the  
USARTx RX complete CPU interrupt flag,  
TCON.URXxIF, and the UxCSR.RX_BYTE bit  
will be asserted when the first stop bit is  
checked OK. If the second stop bit is not OK,  
A UART transmission is initiated when the  
USART  
Receive/Transmit  
Data  
Buffer,  
UxDBUF register is written. The byte is  
transmitted on the TXDx output pin. The  
UxDBUFregister is double-buffered.  
The UxCSR.ACTIVE bit goes high when the  
byte transmission starts and low when it ends.  
When  
UxCSR.TX_BYTE bit is set to 1. The USARTx  
TX complete CPU interrupt flag  
the  
transmission  
ends,  
the  
(IRCON2.UTXxIF) is asserted when the  
UxDBUF register is ready to accept new  
SWRS033E  
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