CC1110Fx / CC1111Fx
13.5.8 DMA Registers
This section describes the SFRs associated with the DMA Controller.
DMAARM (0xD6) – DMA Channel Arm
Bit
Name
Reset
R/W
Description
7
ABORT
0
R0/W
DMA abort. Ongoing DMA transfer or armed DMA channels
will be aborted when writing a 1 to this bit, and at the same
time select which DMA channels to abort by setting the
corresponding, DMAARM.DMAARMnbits to 1
0
1
Normal operation
Abort channels all selected channels
6:5
4
0
0
R0
Not used
DMAARM4
DMAARM3
DMAARM2
DMAARM1
DMAARM0
R/W
DMA arm channel 4
This bit must be set to 1 in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes, the
bit is automatically cleared when the transfer count is reached
3
2
1
0
0
0
0
0
R/W
R/W
R/W
R/W
DMA arm channel 3
This bit must be set to 1 in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes, the
bit is automatically cleared when the transfer count is reached
DMA arm channel 2
This bit must be set to 1 in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes, the
bit is automatically cleared when the transfer count is reached
DMA arm channel 1
This bit must be set to 1 in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes, the
bit is automatically cleared when the transfer count is reached
DMA arm channel 0
This bit must be set to 1 in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes, the
bit is automatically cleared when the transfer count is reached
SWRS033E
Page 111 of 239
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