CC1110Fx / CC1111Fx
13.5.5 DMA Interrupts
generate an interrupt based on the stored
interrupt flag.
Each DMA channel can be configured to
generate an interrupt to the CPU upon
13.5.6 DMA Memory Access
completion of
a
DMA transfer. This is
accomplished by setting the IRQMASK bit in
the channel configuration to 1. When this bit is
set to 1, IRCON.DMAIF=1 will be set to 1
when a transfer is completed. An interrupt
The DMA data transfer is affected by endian
convention. This as the memory system use
Big-Endian in XDATA memory, while Little-
Endian is used in SFR memory. This must be
accounted for in compilers.
request
is
being
generated
if
IEN1.DMAIE=1.The corresponding interrupt
flag in the SFR will be set when the interrupt is
generated.
13.5.7 DMA USB Endianess (CC1111Fx)
When a USB FIFO is accessed using word
transfer, the endianess of the word
read/written can be controlled by setting the
Regardless of the IRQMASK bit in the channel
configuration, DMAIRQ.DMAIFn will be set
upon DMA channel complete. Thus software
should always check (and clear) this register
when rearming a channel with a changed
IRQMASK setting. Failure to do so could
ENDIAN.USBWLE
and
ENDIAN.USBRLE
configuration bits in the ENDIAN register. See
section 13.16 for details.
DMA Trigger
Number
DMA Trigger
Name
Functional
Unit
Description
0
NONE
DMA
No trigger, setting DMAREQ.DMAREQx bit starts transfer
DMA channel is triggered by completion of previous channel
Timer 1, capture/compare, channel 0
Timer 1, capture/compare, channel 1
Timer 1, capture/compare, channel 2
Not in use.
1
PREV
DMA
2
T1_CH0
T1_CH1
T1_CH2
Timer 1
Timer 1
Timer 1
3
4
5
6
T2_OVFL
T3_CH0
T3_CH1
T4_CH0
T4_CH1
ST
Timer 2
Timer 3
Timer 3
Timer 4
Timer 4
Sleep Timer
Timer 2, timer count reaches 0x00
Timer 3, compare, channel 0
7
8
Timer 3, compare, channel 1
9
Timer 4, compare, channel 0
10
11
12
13
14
15
16
17
18
Timer 4, compare, channel 1
Sleep Timer compare
IOC_0
IOC_1
URX0
IO Controller P0_1 input transition15
IO Controller P1_3 input transition16
USART0
USART0
USART1
USART1
USART0 RX complete
USART0 TX complete
USART1 RX complete
USART1 TX complete
Flash data write complete
UTX0
URX1
UTX1
FLASH
Flash
Controller
19
20
21
RADIO
Radio
ADC
ADC
RF packet byte received/transmit
ADC_CHALL
ADC_CH0
ADC end of a conversion in a sequence, sample ready
ADC end of conversion (AIN0, single-ended or AIN0 – AIN1, differential).
Sample ready
15 Trigger on rising edge. P0SEL.SELP0_1and P0DIR.P0_1must be 0
16 Trigger on falling edge. P1SEL.SELP1_3and P1DIR.P1_3must be 0
SWRS033E
Page 107 of 239
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