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CC1111EMK868-915 参数 Datasheet PDF下载

CC1111EMK868-915图片预览
型号: CC1111EMK868-915
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗低于1 GHz的射频系统级芯片(SoC )与MCU,存储器,收发器和USB控制器 [Low-power sub-1 GHz RF System-on-Chip (SoC) with MCU, memory, transceiver, and USB controller]
分类和应用: 存储射频控制器
文件页数/大小: 240 页 / 2823 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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CC1110Fx / CC1111Fx  
byte (optionally 4-byte) sync word and then the  
content of the RFD register. If CRC is enabled,  
the checksum is calculated over all the data  
pulled from the RFD register and the result is  
sent as two extra bytes following the payload  
data. If fewer bytes are written to the RFD  
registers than what the radio expects the radio  
will enter TX_UNDERFLOW state and the  
RFIF.IRQ_TXUNF flag will be set together  
with RFIF.IRQ_DONE. An SIDLE strobe needs  
to be issued to return to IDLE state.  
the optional CRC. The PKTLEN register is  
used to set the maximum packet length  
allowed in RX. Any packet received with a  
length byte with a value greater than PKTLEN  
will be discarded.  
14.8.3 Packet Filtering in Receive Mode  
CC2500 supports two different types of packet-  
filtering: address filtering and maximum length  
filtering.  
14.8.3.1Address Filtering  
If whitening is enabled, everything following  
the sync words will be whitened. This is done  
before the optional FEC/Interleaver stage.  
Setting PKTCTRL1.ADR_CHK to any other  
value than zero enables the packet address  
filter. The packet handler engine will compare  
the destination address byte in the packet with  
the programmed node address in the ADDR  
register and the 0x00 broadcast address when  
PKTCTRL1.ADR_CHK=10 or both 0x00 and  
Whitening  
is  
enabled  
by  
setting  
PKTCTRL0.WHITE_DATA=1.  
If FEC/Interleaving is enabled, everything  
following the sync words will be scrambled by  
the interleaver and FEC encoded before being  
modulated. FEC is enabled by setting  
MDMCFG1.FEC_EN=1.  
0xFF  
broadcast  
addresses  
when  
PKTCTRL1.ADR_CHK=11. If the received  
address matches a valid address, the packet is  
accepted and the RFTXRXIF flag is asserted  
and a DMA trigger is generated. If the address  
match fails, the packet is discarded and  
receive mode restarted (regardless of the  
MCSM1.RXOFF_MODE  
RFIF.IRQ_DONE flag will be asserted but the  
DMA will not be triggered.  
14.8.5 Packet Handling in Receive Mode  
In receive mode, the demodulator and packet  
handler will search for a valid preamble and  
the sync word. When found, the demodulator  
has obtained both bit and byte synchronism  
and will receive the first payload byte.  
setting).  
The  
If FEC/Interleaving is enabled, the FEC  
decoder will start to decode the first payload  
byte. The interleaver will de-scramble the bits  
before any other processing is done to the  
data.  
14.8.3.2 Maximum Length Filtering  
In  
variable  
packet  
length  
mode,  
the  
PKTCTRL0.LENGTH_CONFIG=1,  
PKTLEN.PACKET_LENGTH register value is  
used to set the maximum allowed packet  
length. If the received length byte has a larger  
value than this, the packet is discarded and  
receive mode restarted (regardless of the  
If whitening is enabled, the data will be de-  
whitened at this stage.  
When variable packet length mode is enabled,  
the first byte is the length byte. The packet  
handler stores this value as the packet length  
and receives the number of bytes indicated by  
the length byte. If fixed packet length mode is  
used, the packet handler will accept the  
programmed number of bytes.  
MCSM1.RXOFF_MODE  
setting).  
The  
RFIF.IRQ_DONE flag will be asserted but the  
DMA will not be triggered.  
14.8.4 Packet Handling in Transmit Mode  
Next, the packet handler optionally checks the  
address and only continues the reception if the  
address matches. If automatic CRC check is  
enabled, the packet handler computes CRC  
and matches it with the appended CRC  
checksum.  
The payload that is to be transmitted must be  
written into RFD. The first byte written must be  
the length byte when variable packet length is  
enabled. The length byte has a value equal to  
the payload of the packet (including the  
optional address byte). If fixed packet length is  
enabled, then the first byte written to RFD is  
interpreted as the destination address, if this  
feature is enabled in the device that receives  
the packet.  
At the end of the payload, the packet handler  
will optionally write two extra packet status  
bytes that contain CRC status, link quality  
indication and RSSI value.  
The modulator will first send the programmed  
number of preamble bytes. If data has been  
written to RFD, the modulator will send the two-  
If a byte is received in the RFDregister, and it  
is not read before the next byte is received, the  
SWRS033E  
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